Planarized multi-level interconnect scheme with embedded low-die

Details Planarized multi-level interconnect scheme with embedded low-die Planarized multi-level interconnect scheme with embedded low-die

1995-06-07

1997-04-01

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257774, 257752, 257698, 257700, 257702, 257759, H01L 2928, H01L 2354

Patent

active

056169590

ABSTRACT:
A multi-level interconnect structure and method. A first plurality of interconnect lines (14) is located on an insulator layer (12) of semiconductor body (10). A first layer of low dielectric constant material (20), such as an organic polymer, fills an area between the first plurality of interconnect lines (14a-c) . The first layer of low dielectric constant material (20) has a height not greater than a height of the first plurality of interconnect lines (14). A first layer of silicon dioxide (18) covers the first layer of low dielectric constant material (20) and the first plurality of interconnect lines (14).

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