Planarized gate conductor on substrates with above-surface isola

Details Planarized gate conductor on substrates with above-surface isola Planarized gate conductor on substrates with above-surface isola

1995-04-25

1997-02-25

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257756, 257250, 257510, H01L 2348

Patent

active

056062028

ABSTRACT:
Stringers and depth of focus problems in substrates having above-surface isolation schemes are avoided by applying a first portion of a gate conductor over the entire surface having above-surface isolation, selectively removing the gate conductor from above the isolation features of the above-surface isolation, and overcoating the entire surface with a second portion of gate conductor. The process has particular application to substrates that employ regions having field-shield isolation. An important feature of the invention is drawn to creating structures wherein gate conductor is applied to a substrate including both above-surface and below-surface isolation regions in a manner which leaves the gate conductor planarized over both the above-surface and below-surface regions.

REFERENCES:
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patent: 4424621 (1984-01-01), Abbas et al.
patent: 4570331 (1986-02-01), Eaton, Jr. et al.
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patent: 5122473 (1992-06-01), Mazzali
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patent: 5177028 (1993-01-01), Manning
patent: 5292683 (1994-03-01), Dennison et al.
patent: 5346587 (1994-09-01), Doan et al.
IBM Technical Disclosure Bulletin, "Utilization of Double Poly Nmos Process to Provide Shield for Radiation Hardness" vol. 27 No. 10A Mar. 1985.
IBM Technical Disclosure Bulletin, "Double-Level Polysilicon Memory Cell Process" vol. 19 No. 7 Dec. 1976.

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