Electric heating – Metal heating – By arc
Reexamination Certificate
2001-04-23
2002-07-30
Dunn, Tom (Department: 1725)
Electric heating
Metal heating
By arc
C219S121820, C219S121730
Reexamination Certificate
active
06426478
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the general field of integrated circuit manufacture with particular reference to planarization.
BACKGROUND OF THE INVENTION
Integrated circuits are formed by the deposition of many layers, each of which is shaped into a unique pattern before deposition of the next layer over it. As expected, once several such layers have been laid down, the topmost surface will have become significantly uneven and deposition of subsequent layers cannot be performed without the danger of unintended contact between layers occurring because of inadequate coverage. Thus, it is necessary to have a method for periodically planarizing the surface so that subsequent layers can be built up from a flat base.
For some years now, the preferred method of the prior art for achieving planarization has been chemical mechanical polishing (CMP). While effective, CMP is not without its problems. For example, in structures of the type illustrated in
FIG. 1
(known as damascene wiring) dishing is liable to occur so that trenches in the surface that are to be filled with metal end up being under filled. Additionally, many CMP procedures require an efficient method of end point detection so that over polishing does not occur. Even when it is adequate to perform CMP of the basis of time alone, careful control of this time must be exercised to avoid the same problem.
Another disadvantage of CMP is that it is relatively time-consuming since the time to remove material can be significant. Furthermore careful cleaning of the surface that has just been planarized must be performed to ensure the removal of all debris from the surface. There is thus a need for a planarization process that is not time dependent, that does not introduce dishing, and that leaves no debris behind. Such a process, and the apparatus needed to implement it, constitute the present invention.
A routine search of the prior art was conducted but no references teaching the process or apparatus of the present invention were found. Although several references of interest were encountered, these all teach the application of lasers in a direction that is perpendicular to the surface being treated. For example, Brannon et al. (U.S. Pat. No. 4,508,749) show a method of patterning polyimide films using a UV laser, preferably through a mask. By slightly angling the beam, holes having a positive slope can be formed.
Magee et al. (U.S. Pat. No. 4,758,533) achieve planarization by using a laser to cause local melting of the non-planar surface.
Tessier et al. (U.S. Pat. No. 5,221,426) use a laser to remove thinner portions of a non-planar surface. These cannot dissipate the incident radiation as effectively as the thicker portions so heat up to a higher temperature.
Pan (U.S. Pat. No. 5,236,551) use laser ablation to pattern a polymer layer thereby forming it into a mask which is then used to selectively remove material beneath it in a conventional manner.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a process for planarizing the surface of integrated circuit wafer.
Another object of the invention has been to provide an apparatus suitable for implementing said process.
A further object of the invention has been that said process be equally applicable to planarizing both damascene and conventional wiring surfaces.
Yet another object of the invention has been that said process be significantly faster than processes of the prior art that perform similar functions.
A still further object on the invention has been that the process be self limiting so that end point detection not be required and over polishing not be possible.
These objects have been achieved by directing a high-energy, pulsed laser beam in a direction parallel to the wafer surface while the wafer is rotating. The height of the beam relative to the wafer is carefully controlled thereby enabling the removal of all material above the lower edge of the beam to be removed from the wafer through laser ablation. The method works equally well for removal of metal (as in planarization of damascene wiring) or dielectric (as in planarization of conventional wiring). Once all excess material has been removed (typically requiring about 10-200 seconds) additional operation of the process does no harm so neither end point detection nor precise control of process time are required.
REFERENCES:
patent: 4508749 (1985-04-01), Brannon et al.
patent: 4758533 (1988-07-01), Magee et al.
patent: 5221426 (1993-06-01), Tessier et al.
patent: 5236551 (1993-08-01), Pan
patent: 6040096 (2000-03-01), Kakizaki et al.
patent: 6201253 (2001-03-01), Allman et al.
patent: 6242341 (2001-06-01), Yoo
patent: 6249336 (2001-06-01), Ota
patent: 6354908 (2002-03-01), Allman et al.
Ackerman Stephen B.
Dunn Tom
Johnson Jonathan
Saile George O.
Taiwan Semiconductor Manufacturing Company
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