Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-01-27
2002-10-29
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S435000, C438S692000, C438S693000
Reexamination Certificate
active
06472291
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to a method for planarization of deposited films in a single process step.
2. Description of the Related Art
Semiconductor devices are fabricated by processing layers of materials deposited on a surface of a substrate. One such process includes planarizing a top surface to remove, flatten or smooth the top surface. Planarization techniques are not always uniform across a top surface of a wafer, however, and often depend on the type and density of devices already formed below the layer to be planarized. To attempt to make the planarization process more uniform, preprocessing steps may be employed. In one case, a mask process and an etching process are employed to remove material in selected areas to provide a more uniform layer to be planarized. For example, one method for forming isolation regions includes a deposition of an oxide for a void free fill, a masking and etch step to assist planarization by reducing the oxide over large features and a film removal and planarization by means of a chemical mechanical polish.
One problem with a mask and etch process is that the mask process is typically very expensive. An etch mask must be developed which includes regions which need to be etched and regions which are not be etched. The masking steps, lithographic steps and the etching steps require process time and materials. This makes the preprocessing needed to assist planarization less attractive, especially in sub 0.25 micron technology. However, the elimination of the masking step is generally considered not possible when employing high density plasma deposited films with current chemical-mechanical polishing (CMP) consumables because improved planarization is at the expense of global uniformity.
Therefore, a need exists for a method of depositing and planarizing a dielectric layer with improved global uniformity without the need for preprocessing, such as, for example, masking and etching the dielectric layer before planarization.
SUMMARY OF THE INVENTION
A method for planarizing a dielectric layer on a semiconductor wafer while eliminating a mask and etch step, in accordance with the present invention, includes providing a semiconductor wafer having trenches formed in a trench region of a substrate, and forming a dielectric layer on the semiconductor wafer to fill the trenches whereby up features form on flat surfaces of the wafer. An edge portion of the semiconductor wafer is polished to remove a portion of the dielectric layer about edge portions of the semiconductor wafer. The dielectric layer is polished across the entire semiconductor wafer by employing a single non-stacked polishing pad and a slurry to planarize the trench regions and the up features in a single polish step such that a mask step and etch step for reducing the up features are eliminated from the polishing process.
Another method for planarizing a dielectric layer on a semiconductor wafer while eliminating a mask and etch step, in accordance with the present invention, includes providing a semiconductor wafer having first areas and second areas. The first areas include trenches formed in a substrate of the semiconductor wafer. By depositing and sputtering on a dielectric layer on the semiconductor wafer, the trenches are filled and up features form in the second areas. The sputtering of the dielectric layer is adjusted after the trenches are filled to provide uniformity between a height of the dielectric layer in the first areas and a height of the dielectric layer in the second areas. An edge portion of the semiconductor wafer is polished to remove a portion of the dielectric layer by exerting a bias force against edge portions of the wafer during polishing. The polishing is performed by a single non-stacked polishing pad and a slurry. The dielectric layer is polished across the entire semiconductor wafer by employing the single non-stacked polishing pad and the slurry to planarize the dielectric layer in the first areas and the second areas wherein a mask step and etch step are eliminated from the polishing process.
Yet another method for planarizing a dielectric layer on a semiconductor wafer while eliminating a mask and etch step, in accordance with the present invention, includes providing a semiconductor wafer having an array area including trenches formed in a substrate of the semiconductor wafer and depositing and sputtering on a first oxide layer on the semiconductor wafer to fill the trenches to form trench isolation regions. By depositing and sputtering a second oxide layer on the first dielectric layer at a different bias power than the first oxide layer, a combined height of the first oxide layer and the second oxide layer over the array region is brought closer to a combined height of the first oxide layer and the second oxide layer over up features. An edge portion of the semiconductor wafer is polished to remove a portion of the first and second oxide layers by exerting a bias force against edge portions of the wafer during polishing. The polishing is performed by a single non-stacked polishing pad and a slurry. The dielectric layer is polished across the entire semiconductor wafer by employing the single non-stacked polishing pad and the slurry to planarize the first and second oxide layers wherein a mask step and etch step are eliminated from the polishing process.
In other methods, the step of polishing an edge portion may include the step of exerting a bias force against edge portions of the wafer with a polishing pad during polishing. The polishing pad may include a urethane polishing pad. The step of forming a dielectric layer may include the steps of depositing and sputtering on the dielectric layer to provide a void-free trench fill. The slurry may include a fumed silica particle slurry. The step of forming a dielectric layer may include the step of depositing an oxide layer. The step of forming a dielectric layer may include the step of forming two dielectric layers to reduce a volume difference of the dielectric layer between the trench regions and the flat features by biasing a deposition process for at least one of the two layers. The method may include the step of adjusting the polish rate of the two dielectric layers. The step of depositing a dielectric layer may include the step of depositing an oxide layer by employing a high-density plasma (HDP) deposition.
In still other methods, the step of depositing the first oxide layer and/or the second oxide layer may include the step of depositing the first oxide layer by a high-density plasma (HDP) process. The method may include the step of adjusting the polish rate of the first and second oxide layers. The bias power is preferably higher for the first oxide layer than the bias power for the second oxide layer.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 5212114 (1993-05-01), Grewal et al.
patent: 5643823 (1997-07-01), Ho et al.
patent: 5747866 (1998-05-01), Ho et al.
patent: 5763315 (1998-06-01), Benedict et al.
patent: 5804490 (1998-09-01), Fiegl et al.
patent: 5851899 (1998-12-01), Weigand
patent: 5854126 (1998-12-01), Tobben et al.
patent: 5880007 (1999-03-01), Varian et al.
patent: 5923993 (1999-07-01), Sahota
patent: 6037237 (2000-03-01), Park et al.
patent: 6090714 (2000-07-01), Jang et al.
patent: 6180525 (2001-01-01), Morgan
patent: 6197660 (2001-03-01), Jang et al.
patent: 6261957 (2001-07-01), Jang et al.
Bailey Scott W.
Davis Jonathan P.
Page Joseph E.
Braden Stanton
Infineon Technologies North America Corp.
Pompey Ron
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