Planarization process for trench isolation in integrated circuit

Details Planarization process for trench isolation in integrated circuit Planarization process for trench isolation in integrated circuit

1991-06-28

1992-12-29

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437228, 437978, 148DIG50, H01L 2176

Patent

active

051751224

ABSTRACT:
A method of planarizing the surface of a silicon wafer of the type employing trench isolation is disclosed where the trenches and active areas of wafer surface may be of varying widths. The trenches and active areas are covered with a conformal coating of silicon oxide, and, according to one embodiment, this coating is subjected to an etch to leave sidewall spacers of oxide at the sidewalls of the trenches, then a second conformal coating of oxide is applied. A first layer of photoresist is applied to the face and patterned to leave photoresist only in the wider trenches. According to another embodiment the remaining photoresist of the first layer is reflowed by a heat treatment to account for any misalignment or the like. A second layer of photoresist is applied, then etched back to the conformal coating on the active areas, leaving some resist in narrow trenches. A third layer of photoresist is applied and then the three layers of photoresist plus oxide are simultaneously etched back to the level of the tops of the active areas, leaving a substantially planar surface where there is a minimum of variation in height in the various areas of differing trench and active area widths.

REFERENCES:
patent: 4505025 (1985-03-01), Kurosawa et al.
patent: 5077234 (1991-12-01), Scoopo et al.
Daubenspeck et al., "Planarization of ULSI Topography over Variable Pattern Densities", J. Electrochem. Soc., Feb. 1991, pp. 506-509.
Fuse et al., "A New Isolation Method with Boron-Implanted Sidewalls for Controlling Narrow-Width Effect", IEEE Trans. on Electron Dev., Feb. '87, p. 356.
Shibata et al., "A Simplified Box (Buried-Oxide) Isolation Technology", IEDM, 1983, pp. 27-30.
Davari et al., "A Variable-Sized Shallow Trench Isolation (ST1) Technology with Diffused Sidewall Doping for Submicron CMOS", IEDM '88, pp. 92-95.
Sheldon et al., "Application of a Two-Layer Planarization Process to ULSI Intermetal Dielectric and Trench Isolating Processes", IEEE Tr. on Semicond. Mfgs., 1988, pp. 140-145.
Schiltz et al., "Two-Layer Planarization process", J. Electro Chem Soc., Solid State Sci. and Tech., Jan. '86, pp. 178-181.
Yamabe et al., "Nonplanar oxidation and Reduction of Oxide Leakage Currents at Silicon Corners by Rounding-Off Oxidation", IEEE Tr. on Elect. Dev., Aug. '87, p. 1681.

Affiliated with

Also associated with

Rating

Planarization process for trench isolation in integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Planarization process for trench isolation in integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Planarization process for trench isolation in integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1886850