Planarization process

Details Planarization process Planarization process

1998-08-11

2002-05-21

Hiteshew, Felisa (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S692000, C451S285000

Reexamination Certificate

active

06391779

ABSTRACT:

BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to the processing of semiconductor substrates, such as silicon wafers, which are used in the manufacture of semiconductor devices. The present invention more specifically relates to the polishing or planarizing of the surfaces of semiconductor substrates using a process known as chemical mechanical planarization (CMP). Methods disclosed herein improve the result of CMP processes when performed on an apparatus known as a linear track polisher, or on an apparatus known as a rotational polisher.
2. The Relevant Technology
In the fabrication of integrated circuits, numerous integrated circuits are typically constructed simultaneously on a single semiconductor substrate. To reduce the cost of producing individual semiconductor devices, it has long been an objective of semiconductor manufacturers to increase the number of devices on a single substrate. For a period of time this was accomplished primarily by a continual scaling down of the geometries of individual active devices within the integrated circuits.
In the context of this document, the term “semiconductor substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term “substrate” refers to any supporting structure including but not limited to the semiconductor substrates described above. A substrate may be made of silicon, gallium arsenide, silicon on sapphire (SOS), epitaxial formations, germanium, germanium silicon, diamond, silicon on insulator (SOI) material, selective implantation of oxygen (SIMOX) substrates, and/or like substrate materials. Preferably, the substrate is made of silicon which is typically single crystalline.
The scaling of active devices eventually became less profitable as the limitations of the circuit speed and maximum functional density came to depend more on the characteristics of the electrical interconnects of the devices than on the scale of the devices themselves. In addition, the aspects of silicon utilization, chip costs, and ease of flexibility of integrated circuit design were also adversely affected by electrical interconnect technology restrictions. The approaches to lifting these limitations have involved the implementation of vertical stacking or integration of devices and their associated electrical interconnections, commonly referred to as multilevel interconnect (MLI) schemes. In MLI schemes, individual conductor layers are separated by dielectric layers which are sandwiched between the conductor layers. These dielectric layers are typically oxide or nitride layers which are grown or deposited on the substrate and are known as interlevel dielectrics (ILD).
One drawback of multilevel interconnection is a loss of topological planarity. Loss of planarity results in associated problems in photolithography and etch, as well as other problems. To alleviate these problems, the substrate is planarized at various points in the process to minimize non-planar topography and its adverse effects. As additional levels are added to multilevel interconnection schemes and circuit features are scaled to sub-micron dimensions, the required degree of planarization increases. Such planarization can be performed on either the conductor or the interlevel dielectric layers to remove high topography or to remove embedded particles.
The polishing process may also involve the introduction of a chemical slurry to facilitate higher removal rates and selectivity between films of the semiconductor surface. This polishing process is often referred to as chemical mechanical planarization (CMP). The chemical slurry used in CMP contains abrasives therein to assist in the mechanical removal of the layer. When fixed abrasives are incorporated into a polishing pad in a CMP process, abrasives are not needed in the chemical slurry, and a liquid ammonium solution can be used in lieu of a slurry while dripped onto the polish pad during the polishing process.
CMP is implemented in dielectric layer planarization by growing or depositing a layer, such as oxide or nitride, on the semiconductor substrate, typically to fill in contact regions or trenches between metallization lines, and then removing the excess dielectric material using the CMP process, until a flat, smooth surface is achieved.
CMP processes have been used in the semiconductor industry for many years. A primary application of CMP processing has been the polishing of silicon substrates, such as silicon wafers, before active device fabrication. Only in recent years has the CMP process been applied to planarizing metallization layers and their inter-dielectric layers, and these new applications are the result of integrated circuit device fabrication processing scaling down to deep submicron geometries. A major hurdle to overcome in adapting CMP processes to the planarization of metallization and dielectric layers is that the typical thicknesses of the layers being planarized, and the variations in final thicknesses allowed over the entire surface area of the layers, are smaller than the critical dimensions associated with earlier semiconductor applications.
In addition to the need for tight tolerances in the planarizing of semiconductor metal and dielectric layers, there is a continuing need to reduce the amount of process time associated with the CMP material removal steps.
A type of apparatus known as a rotational polisher has been used widely in the practice of chemical mechanical planarization. The rotational polishing process involves under controlled pressure and temperature. An example of such an apparatus is the Model 372 Polisher manufactured and distributed by IPEC Westech Systems, of San Jose, Calif.
FIG. 1
shows a rotational polisher
11
having a rotatable polishing platen
12
, a substrate polishing head assembly
14
and a chemical supply system
18
. Platen
12
is typically covered with a replaceable, relatively soft material
16
such as polyurethane.
Substrate polishing head assembly
14
holds semiconductor substrate
10
adjacent to platen
12
. Substrate polishing head assembly
14
includes a motor (not shown) for rotating the polishing head and semiconductor substrate
10
. Substrate polishing head assembly
14
further includes a polishing head displacement mechanism (not shown) which moves the substrate
10
back and forth across the platen
12
as it is rotating. Substrate polishing head assembly
14
applies a controlled downward pressure to semiconductor substrate
10
to hold semiconductor substrate
10
against rotating platen
12
so that a continuous polishing surface
34
on rotating
12
platen polishes semiconductor substrate
10
. Chemical supply system
18
introduces a polishing slurry (not shown) to be used as an abrasive medium between platen
12
and semiconductor substrate
10
.
Chemical mechanical planarization (CMP) using a rotational polishing system is a conventional polishing process. Examples of CMP are seen in U.S. Pat. No. 4,680,893 issued on Jul. 21, 1987 to Cronkhite et al., U.S. Pat. No. 5,142,828 issued on Sep. 1, 1992 to Curry, II, and U.S. Pat. No. 5,514,245 issued on May 7, 1996 to Doan et al. The Cronkhite et al. reference teaches polishing bare silicon wafers after they have been cut from a silicon ingot. The polishing requires two similar polishing steps using two dissimilar pads and two dissimilar polishing pressures. The Curry, II reference teaches removal of a defective metallization layer by a single CMP process, followed by formation of a replacement defect-free metallization layer. The single CMP process of Curry, II uses a single polishing pad at a single pressure on the defective metallization layer to remove the same. The Doan et al. reference teaches two CMP steps for planarizing a dielectric layer on a wafer. Like the Cronkhite et al

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