Planarization of silicon semiconductor devices

Details Planarization of silicon semiconductor devices Planarization of silicon semiconductor devices

1986-12-03

1988-03-22

Niebling, John F.

Fishing, trapping, and vermin destroying

20419223, 2041923, 20419222, 156653, 1566591, 156662, 427255, 430313, 430317, C23C 1434, H01L 21308, H01L 21324

Patent

active

047326581

ABSTRACT:
A substantially planar surface is provided over a silicon semiconductor device by depositing a silicate glass, heating the silicate glass so it reflows, bias sputtering a dielectric layer over the reflowed glass, depositing a photoresist over the dielectric layer and etching away the photoresist and enough of the dielectric to provide a substantially planar surface of the dielectric material. Quartz is the preferred dielectric material.

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S. Shanfield, et al., "Process Characterization of PSG and BPSG Plasma Deposition", LFE Corporation, Clinton, MA 01510.
C. Ramiller et al., "Borophosphosilicate Glass for Low Temperature Reflow".
Avigal, "Inter-Metal Dielectric and Passivation-Related Properties of Plasma BPSG", Intel Corporation, Santa Clara, CA.
J. E. Tong et al., "Process and Film Characterization of PECVD Porophosphosilicate Films for VLSI Applications", Solid St. Tech., 1984.

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