Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-07-12
2003-11-11
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S221000, C438S296000, C438S437000, C438S692000, C257S506000, C257S510000
Reexamination Certificate
active
06645825
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of a planarized structure of shallow trench isolation (STI) embedded in a semiconductor substrate.
(2) Description of Related Art
As semiconductor integrated circuits progress toward greater micro-miniaturation, active devices are packed into ever smaller areas and electrical isolation between active devices becomes an extremely important issue. Shallow trenches filled with insulating material have proven to be most desirable for isolating active devices. At the same time in the fabrication of semiconductor integrated circuits, substrate surface planarity is of extreme importance and CMP (Chemical Mechanical Polishing) has been developed to produce smooth topographies on surfaces deposited on semiconductor substrates. When CMP (Chemical Mechanical Polishing) is applied to trench isolation technology the CMP process removes insulating material from the surface of the active semiconductor areas and retains insulating material in the trenches. However, various combinations of trench width and active area width occur across the surface of the semiconductor substrate and these factors affect the uniformity of removal of the CMP process. Furthermore, variations in circuit density cause variations in percentages of substrate area occupied by trenches and by active semiconductor. Because of these varying pattern densities, a sufficient degree of uniform planarization sometimes is not achieved by state-of-the-art CMP processes. Therefore, a challenge in the industry is to provide a means of formation of planarized isolation trenches, where such trench fill process and planarization process result in the desired uniformity and have both minimal cost and high manufacturing yield.
U.S. Pat. No. 5,942,449 entitled “Method for Removing An Upper Layer Of Material From A Semiconductor Wafer” granted Aug. 24, 1999 to Scott G. Meikle describes a two-step method of removing and planarizing a layer on a semiconductor substrate, in which the first step removes a substantial portion of the layer by a chemical etching process and the second step removes the remaining portion of the layer by a CMP process which simultaneously planarizes the layer.
U.S. Pat. No. 5,736,462 entitled “Method Of Etching Back Layer On Substrate” granted Apr. 7, 1998 to Hiroshi Takahashi et al. describes a method of endpoint detection for CMP (Chemical Mechanical Polishing) whereby an intermediate layer under the layer being polished has a larger or smaller polish rate. A signal derived from the polishing tool detects when this intermediate layer is being polished and this signal is used to determine CMP endpoint.
The present invention is directed to a novel method of controlling CMP (Chemical Mechanical Polishing) of STI (Shallow Trench Isolation), which results in improved planarization uniformity. The method of the present invention requires less CMP processing time, has lower cost than conventional CMP methods and produces a polished surface having superior planarity.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved method of forming planarized isolation trenches for use in semiconductor integrated circuits.
A more specific object of the present invention is to provide an improved method of forming planarized isolation trenches for use in semiconductor integrated circuits, wherein the chemical-mechanical polishing process results in superior planarization uniformity.
Another object of the present invention is to provide an improved method of forming planarized isolation trenches for use in semiconductor integrated circuits, wherein the chemical-mechanical polishing process results in superior planarization uniformity, has high manufacturing yield and low manufacturing cost.
In accordance with the present invention, the above and other objectives are realized by using a method of fabricating a planarized structure on a semiconductor substrate, wherein an insulating material is embedded in a trench formed in the semiconductor substrate, the method comprising the following steps: providing a semiconductor substrate having a layer of silicon nitride formed thereon and at least one trench formed through the layer of silicon nitride and into the semiconductor substrate; depositing a layer of insulating material onto said layer of silicon nitride and into said at least one trench formed through the layer of silicon nitride and into the semiconductor substrate; chemical-mechanical polishing the layer of insulating material by a first CMP step comprising chemical-mechanical polishing until exposure of said silicon nitride layer is detected by an endpoint detecting device; selecting an overpolish thickness based on the percentage of substrate area occupied by said trench; and chemical-mechanical polishing the layer of insulating material by a second CMP step which removes said overpolish thickness based on the percentage of substrate area occupied by said trench.
REFERENCES:
patent: 5736462 (1998-04-01), Takahashi et al.
patent: 5942449 (1999-08-01), Meikle
patent: 6080670 (2000-06-01), Miller et al.
patent: 6087262 (2000-07-01), Yang et al.
Kuan Tong-Hua
Lan Chin Kun
Wang Ting Chun
Wang Ying-Lang
Ackerman Stephen B.
Bowers Charles
Lee Hsien-Ming
Saile George O.
Taiwan Semiconductor Manufacturing Company
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