Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1997-04-07
1999-07-20
Fourson, George
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438692, 438734, 438743, 438756, H01L 2176
Patent
active
059267224
ABSTRACT:
A new method for planarization of shallow trench isolation is disclosed by using wet selective etching. The formation of the shallow trench isolation described herein includes a pad layer, a silicon nitride layer formed on a semiconductor substrate. A PE-TEOS oxide layer is subsequently formed on the silicon nitride layer. Then a shallow trench is created by photolithography and dry etching processes to etch the PE-TEOS oxide layer, the silicon nitride layer and the pad layer. Then, the photoresist is removed, an ozone-TEOS layer is form in the shallow trench and on the PE-TEOS oxide layer for the purpose of isolation. A wet selective etching is used to etch the ozone-TEOS layer. A CMP is performed to make the surface of the substrate with a planar surface. Then, a thermal annealing is used for densification of the ozone-TEOS layer and for forming a lining oxide to improve the isolation of the shallow trench isolation.
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Jang S. M.
Yu C. H.
Fourson George
Taiwan Semiconductor Manufacturing Co. Ltd.
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