Planarization of integrated circuit surfaces through selective p

Details Planarization of integrated circuit surfaces through selective p Planarization of integrated circuit surfaces through selective p

1974-06-17

1976-08-24

Esposito, Michael F.

Adhesive bonding and miscellaneous chemical manufacture

Methods

156 17, 427 93, 427 94, 427 96, 427259, 427271, 427273, 427331, 427335, 427336, 204192, 96 36, 96 362, B05D 304, B05D 312

Patent

active

039765245

ABSTRACT:
An integrated circuit substrate surface, particularly a surface of electrically insulative material, having a pattern of elevated areas and a complementary pattern of unelevated areas is planarized by forming the photoresist pattern in registration with the pattern of unelevated areas, the photoresist pattern having narrower lateral dimensions than said elevated pattern whereby registration is facilitated, flowing the photoresist pattern to laterally expand the photoresist to cover and thereby mask the unelevated areas, and etching to lower the elevated areas which remain uncovered by the photoresist.

REFERENCES:
patent: 2294479 (1962-09-01), Peter
patent: 3475194 (1969-10-01), Samour
patent: 3503124 (1970-03-01), Warlass
patent: 3737499 (1973-06-01), Kamena
patent: 3779806 (1973-12-01), Gipstein
patent: 3799777 (1974-03-01), O'Keefe
patent: 3804738 (1974-04-01), Lechaton
patent: 3868723 (1975-02-01), Lechaton

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