Planarization of integrated circuit surfaces through selective p

Details Planarization of integrated circuit surfaces through selective p Planarization of integrated circuit surfaces through selective p

1976-06-14

1977-07-26

Rutledge, L. Dewayne

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

148175, 357 73, H01L 21308

Patent

active

040381102

ABSTRACT:
An integrated circuit substrate surface, particularly a surface of electrically insulative material, having a pattern of elevated areas and a complementary pattern of unelevated areas is planarized by forming the photoresist pattern in registration with the pattern of unelevated areas, the photoresist pattern having narrower lateral dimensions than said elevated pattern whereby registration is facilitated, flowing the photoresist pattern to laterally expand the photoresist to cover and thereby mask the unelevated areas, and etching to lower the elevated area which remain uncovered by the photoresist.

REFERENCES:
patent: 3681153 (1972-08-01), Clark et al.
patent: 3783047 (1974-01-01), Paffen et al.
patent: 3883889 (1975-05-01), Hall
patent: 3961999 (1976-06-01), Antipov
patent: 3966514 (1976-06-01), Feng et al.

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