Planarization of ceramic substrates using porous materials

Details Planarization of ceramic substrates using porous materials Planarization of ceramic substrates using porous materials

2001-12-21

2003-12-23

Barr, Michael (Department: 1762)

Coating processes

Electrical product produced

C427S126300, C427S402000, C427S419100, C427S419200, C427S243000

Reexamination Certificate

active

06667072

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of Invention
This invention mainly provides a concept of using porous materials on ceramic substrate planarization. This planarized substrate can be utilized in the fields of electronic information communication, opto-electronics and display.
2. Description of the Prior Art
It is an important postulation for having a planar surface for the thin-film processes. The high cost is due to two main aspects. The first aspect is due to the high substrate-polishing cost based on either silicon wafer or glass manufacture factory. The second aspect is the high fabrication cost on the flattening technology as a key technology to produce metallized module IC.
At present, some common smoothing techniques include mechanical polishing, chemical mechanical polishing, chemical etching, high temperature reflow through borophosphosilicate, and spin coating. Thin film's roughness and adherence are often limited after surface treatment at which may additionally complicate the processing and increase the cost. The prior arts are shown as following:
Prior Art
Focal technique
Defect
US4944836:
A method for VLSI
The chemical reagent
Chem-mech
and ULSI (Ultra-Large
used in CMP method
polishing (CMP)
Semiconductor
is expensive and hard
method for
Integration) offer
to be controlled during
producing coplanar
“global
the process.
metal/insulator films
planarization”.
And it is also lack of
on a substrate
The combination of
terminate detecting
mechanism polishing
system.
and chemical reagent
Finally, a trace of
to flatten silicon
contaminant may be
wafer. More than
observed in polish
94% of rough surface
process.
as consequence
can be planarized
by CMP method.
Silicon Processing
Surface of
The spin on glass
for the VLS:
silicon wafer
processing can
Basics of Thin Films
recovered by a liquid
provide only local
solution via spin
planarization.
coating method, after
Disadvantage may be
heat treatment there-
observed for example
fore a planar dielectric
like the formation of
layer can be formed.
particles, film crack,
A deep gap fill capa-
delamination and
bility on such surface
exhausted
can be obtained by
out-gassing.
SOG method.
Solid State Technology:
A layer of low glass
Both B
2
H
6
and PH
3
Viscous Behavior of
transition temperature
are chemically toxic
Phosphosilicate,
materials BPSG
and are employed in
Borophosphosilicate
deposition on a surface
BPSG processing.
and Germano-
by CVD method. At
This planarization can
phosphosilicate
high temperature
be applied to the
Glasses in VLSI
reflow BPSG on the
planarizing dielectric
Processing.
substrate and then
barrier layer before
resulting surface
metallization. After
planarization.
the coverage of Al
metal layer however
BPSG reflowing
process cannot be
applied.
Solid State
Excess thick layer of
Only a partial
Technology:
SiO
2
deposited. The
planarization can be
Chemical Etching
application of
obtained by chemical
anisotropic-etch
etching method. It is
method can then etch
not applicable.
back SiO
2
layer to
desired thickness.
SUMMARY OF THE INVENTION
Conclusively, the main purpose of this invention can solve the above-mentioned defects (film crack, delamination, etc.). In order to overcome these problems, this invention provides a concept of using porous materials on ceramic substrate planarization, wherein the nanostructure layer provides the required surface smoothness upon the ceramic substrates and enhances the adhesion between substrate and subsequent thin-film layers.
This invention can tremendously reduce the production cost due to its simple production process.
In order to achieve the said objectives, the invention provides a method of using porous materials on ceramic substrate planarization. This invention sustains a surface flattening method by employing the participation of porous materials such as zeolites, zeolite-like, mesoporous and mesoporous composites. Meanwhile, this invention results in good affinity for the electrical and dielectric properties, for instance, thermal conductivity, electrical insulation, dielectric and other required properties for integrated components. Due to a good polarization obtained, this invention permits furthermore an intensive binding between thin films and electronic materials.


REFERENCES:
patent: 5952040 (1999-09-01), Yadav et al.
patent: 6432472 (2002-08-01), Farrell et al.
patent: 6503382 (2003-01-01), Bartlett et al.
patent: 2002/0167981 (2002-11-01), Eisenbeiser

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