Planarity verification system for integrated circuit test probes

Details Planarity verification system for integrated circuit test probes Planarity verification system for integrated circuit test probes

1997-12-12

2000-03-28

Ballato, Josie

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324754, G01R 3100

Patent

active

060436689

ABSTRACT:
A planarity verification system for proper positioning of testing probes comprises a plurality of electrical leads configured for connection to testing probes, an indicator electrically coupled to each of the leads, and a power source. One of the power source terminals is electrically coupled to the leads through the indicators and the other terminal is electrically coupled to a metalized surface such as a wafer to bias the surface. Each electrical lead forms part of a completed current path between the power source terminals when a testing probe contacts a biased surface and directs current through an associated indicator to provide an indication.

REFERENCES:
patent: 4261762 (1981-04-01), King
patent: 4508161 (1985-04-01), Holden
patent: 5539676 (1996-07-01), Yamaguchi
patent: 5594357 (1997-01-01), Nakajima
patent: 5642056 (1997-06-01), Nakajima et al.
patent: 5731708 (1998-03-01), Sobhani
patent: 5861759 (1999-01-01), Bialobrodski et al.

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