Planar void free isolation structure

Details Planar void free isolation structure Planar void free isolation structure

1985-03-14

1987-07-14

Larkins, William D.

Metal treatment

Stock

Ferrous

357 54, 357 55, 357 59, 148DIG50, 148DIG85, 148DIG122, 148DIG131, H01L 2195, H01L 2704

Patent

active

046806148

ABSTRACT:
A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation:

REFERENCES:
patent: 4256514 (1981-03-01), Pogge
patent: 4400411 (1983-08-01), Yuan et al.
patent: 4473598 (1984-09-01), Ephrath et al.
patent: 4493740 (1985-01-01), Komeda
patent: 4526631 (1985-01-01), Silvestri et al.
J. Riseman, "Deep Dielectric Isolation", IBM Tech Discl Bull, vol. 23, No. 8, Jan. 1981, pp. 3689-3690.
Endo et al, "Novel Device Isolation Technology with Selective Epitaxial Growth", IEDM 1982, pp. 241-244.

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