Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Light responsive structure
Reexamination Certificate
1999-04-19
2001-05-08
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Light responsive structure
C257S184000, C257S186000, C257S199000
Reexamination Certificate
active
06229162
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a planar-type avalanche photodiode (referred to as APD hereinafter) that has high sensitivity and a wide dynamic range as well as high reliability suitable for use in high-speed optical fiber communication.
2. Description of the Prior Art
As a high-speed high-sensitivity optical receiver for use in the next generation optical fiber communication system, a planar-type superlattice APD shown in
FIG. 6
has been reported (IEEE Photonics Technol. Lett., Vol.8, pp.827-829, 1996; Japanese Patent Application No.299996/1994/Japanese Patent Application Laid-open No. 312442/1995).
In such a device that is a first example of the prior art herein, a higher gain-bandwidth product (GB product) and lower noise are brought about through the enhancement effect of an InAlAs/InAlGaAs superlattice multiplication layer on the ionization rate ratio. At the same time, higher reliability is also produced therein by a structure in which only a stable InP planar pn-junction is exposed to the surface.
In such a conventional planar-type superlattice APD, a Ti-implanted guard-ring is formed in order to suppress edge-multiplication. The operation principle thereof is as follows. Due to Ti implantation, the p-concentration in a p-InP field buffer layer of the guard-ring section decreases locally. Taking advantage of this decrease, the punch-through voltage of a depletion layer to a photo-absorption layer in the guard-ring section is reduced, as shown in
FIG. 5
, and thereby the bias voltage applied to an edge section is spread over the photo-absorption layer section, suppressing the edge electric field increase.
If the spreading of the voltage over the photo-absorption layer hereat is excessive, however, the field strength of the photo-absorption layer in the edge section becomes too high and passes over the tunneling dark current limit (normally 200 kV/cm) and the dark current of the APD device is increased. This indicates that there exists the optimum value for the dose of Ti implantation. Under such conditions, in order to provide a wider dynamic range for the high frequency response of the APD, in other words, to obtain a high frequency response (a 3 dB bandwidth above 10 GHz) even at a low bias and a low multiplication factor M (M>~1.5), the maximum field strength in the photo-absorption layer at the time of breakdown should be set as high as ~150 kV/cm or so. In this case, however, when the bias voltage is spread over the photo-absorption layer in order to bring about the above-mentioned guard-ring effect, there arises another problem that the tunnel dark current is liable to generate in the photo-absorption layer section of the guard-ring because the first setting of the field strength itself is already relatively high.
Accordingly, the conventional planar-type superlattice APD has a problem that a range of the optimum value for the dose of Ti implantation mentioned above tends to become small, depending on the setting of the maximum field strength in the photo-absorption layer.
SUMMARY OF THE INVENTION
In light of the above problems, an object of the present invention is to provide a planar-type APD that does not have such problems as described above and that has a greater manufacturing tolerance, high reliability, high sensitivity as well as a wide dynamic range.
In accordance with an aspect of the present invention, there is disclosed a planar-type avalanche photodiode; having on a semiconductor substrate:
a layered structure comprising a first conductive-type semiconductor buffer layer, a first conductive-type semiconductor photo-absorption layer, a first conductive-type semiconductor field buffer layer, a semiconductor multiplication layer, a second conductive-type semiconductor cap layer and a second conductive-type semiconductor contact layer;
a first conductive-type acquired region, in a peripheral section of a photo-sensitive region, from the surface down to a level at least deep enough to reach said first conductive-type semiconductor field buffer layer; and
a ring-shaped isolation trench region, between the conductive-type semiconductor cap layer in said photo-sensitive region and said first conductive-type acquired region, with a depth that is equivalent to a sum of thicknesses of said second conductive-type semiconductor contact layer and cap layer; wherein:
a ring-shaped region of the second conductive-type semiconductor cap layer that is inscribed in said ring-shaped isolation trench and located in the periphery of the photo-sensitive region is formed thin to have a thickness equal to or less than the thickness of said semiconductor multiplication layer; and
the first conductive-type semiconductor field buffer layer located directly under the ring-shaped cap region, together with a peripheral region in the field buffer layer, is formed to have a lower carrier concentration than the first conductive-type field buffer layer in said photo-sensitive region.
In accordance with another aspect of the present invention, there is disclosed another planar-type avalanche photodiode; having on a semiconductor substrate:
a layered structure comprising a first conductive-type semiconductor buffer layer, a first conductive-type semiconductor photo-absorption layer, a first conductive-type semiconductor field buffer layer, a semiconductor multiplication layer, a second conductive-type semiconductor cap layer and a second conductive-type semiconductor contact layer;
a first conductive-type acquired region, in a peripheral section of a photo-sensitive region, from the surface down to a level at least deep enough to reach said first conductive-type semiconductor field buffer layer;
a ring-shaped isolation trench region, between the conductive-type semiconductor cap layer in said photo-sensitive region and said first conductive-type acquired region, with a depth that is more than the depth of said second conductive-type semiconductor contact layer and less than the depth of said cap layer; and, in addition,
a highly-resistive region in an outer ring-shaped region that is formed, by dividing said ring-shaped isolation trench into two ring-shaped concentric regions, to a depth that reaches said semiconductor multiplication layer; wherein:
said first conductive-type semiconductor field buffer layer located directly under an internal ring-shaped region, together with a peripheral region in the field buffer layer, is formed to have a lower carrier concentration than the first conductive-type field buffer layer in said photo-sensitive region.
Further, the planar-type avalanche photodiode of the present invention is characterized in that a first etching stop layer is set between said semiconductor multiplication layer and second semiconductor cap layer; or characterized in that said second conductive-type cap layer is divided in the direction of layers and a second and a third etching stop layers are set in between.
Further, the planar-type avalanche photodiode of the present invention is characterized in that said second conductive-type semiconductor cap layer is divided in the direction of the layers and the first etching stop layer is set in between; or characterized in that said semiconductor multiplication layer is composed of a material selected from the group consisting of InAlAs, InAlAsP, semiconductor alloy compounds containing InAlAs, an InAlAs/InAlGaAs superlattice, an InAlAs/InGaAs superlattice and an InAlAs/InGaAsP superlattice; or characterized in that said second conductive-type semiconductor field buffer layer is composed of a material selected from the group consisting of InP, InGaAsP, InAlAs, InAlGaAs and InAlAsP; or characterized in that the first etching stop layer in said device structure is composed of InP; or characterized in that the second etching stop layer in said device structure is composed of InP and the third etching stop layer therein is composed of InGaAs or InAlGaAs; or characterized in that said highly-resistive region is formed by ion implantation of any selected among Ti, Fe, Co, O, H
Kang Donghee
NEC Corporation
Thomas Tom
Young & Thompson
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