Planar transferred electron logic device with improved biasing m

Details Planar transferred electron logic device with improved biasing m Planar transferred electron logic device with improved biasing m

1976-12-14

1978-04-25

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 3, 331107G, 307213, H01L 2704, H03K 326

Patent

active

040865010

ABSTRACT:
A planar transferred electron logic device comprising a substrate of substantially insulating material and a layer of semiconductor material which exhibits a differential negative resistance through the "transferred electron effect" upon application of an electric field above threshold level. Spaced anode, cathode and gate terminals are located on the semiconductor layer. The anode and cathode terminals are biased slightly below threshold creating thereby a reverse bias on the gate terminal. An input signal is applied to the gate terminal to trigger the device causing the formation of domains. The terminals are biased by an improved biasing circuit to reduce the magnitude of the reverse bias and the input signal to enhance the trigger sensitivity and stability of the device.

REFERENCES:
patent: 3566306 (1971-02-01), Esposito et al.
patent: 3588736 (1971-06-01), McGroddy
patent: 3706014 (1972-12-01), Dean
patent: 3959807 (1976-05-01), Upadhyayula et al.
patent: 3991328 (1976-11-01), Upadhyayula et al.

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