Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1998-11-23
2001-09-04
Jones, Deborah (Department: 1775)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S690000, C257S700000, C257S737000, C257S738000, C428S209000, C428S212000, C428S469000, C428S701000, C428S901000
Reexamination Certificate
active
06285080
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to new planar substrates that are metallized and embedded with material to minimize the camber and method thereof The invention also relates to the fabrication of multilayer ceramic (MLC) substrates for packaging electronic devices. More particularly, this invention relates to the fabrication of thin and small ceramic packages which do not need post-sintering processing to control the flatness of the sintered product.
BACKGROUND OF THE INVENTION
Ceramic packages are needed by the electronic industry to provide a required level of electrical interconnection between an electronic device, such as, a chip, and a board, such as, a plastic board.
The ceramic substrates have the ability to provide a high density interconnection surface on the top layer which connects to the integrated circuit chip and a lower density interconnection surface on the bottom layer which connects to the board. This interconnection density is particularly high when flip-chip solder balls, such as, C4 (Control Collapse Chip Connection) are used on the top surface and ball grid array (BGA) technology is used on the bottom surface of the ceramic substrate or package.
In addition to the two external layers described earlier, the ceramic package typically has several internal layers which provide distinct electrical functions. The first function is to provide power to the electronic device, such as, a chip, and this function is done by the voltage plane layers. The second function is to provide connectivity between the signal output from the integrated circuit chip to the signal lines on the board, and this function is done by the redistribution layers. In some cases both functions may be provided in the same layer. This may be done for a variety of reasons, such as, when it is necessary to minimize the package layer count.
The number of layers required by the ceramic package to provide the specified electronic connectivity function is dependent both on the complexity of the integrated circuit chip and on the level of integration that the thick film processing line can achieve when building the ceramic package.
Continuous advancement of the thick film processing capabilities has been reducing the number of layers needed to provide the required electrical connectivity in the ceramic package. Also, the introduction of BGA to the BSM (bottom surface metallurgy) side which connects to the board allows significant reduction in the size of the ceramic package required when compared to similar packages manufactured with, for example, pins.
Thus, the market trend is moving toward ceramic packages which are small and thin when the connectivity function is required to package a single integrated circuit chip. The reduction in dimension is also followed by a reduction in the cost of processing such ceramic packages, as more units can be fabricated on the same space previously taken during the fabrication of larger ceramic packages.
Of particular concern in processing the smaller ceramic packages is the control of the package camber during sintering. If the ceramic package is not sufficiently flat after sintering, it needs to be discarded or reworked, and in both cases the product cost is increased significantly, because of the relatively high rework cost; the increased need to characterize the product; and/or the replacement cost associated with discarded product.
The flatness requirements of a ceramic package are driven by the processes used after the sintering process. Typically, the top surface of a ceramic package requires a flatness of under 30 microns in the area where the electronic device will be connected to the ceramic package. This flatness requirement is known as the via bulge specification.
The bottom surface typically requires a flatness of under 150 microns through the area where the ball grid array (BGA) is located. This flatness requirement is known as the substrate camber specification.
In large and thick ceramic packages, the ceramic via bulge is a weak function of the substrate bottom surface and a strong function of the substrate internal wiring design. A large camber at the bottom of the package or high via bulge at the top will result in electrical shorts or opens in the final assembled module. However, as the package becomes small and thin and the integrated circuit chip becomes large, a larger fraction of the substrate camber becomes the package via bulge because in thin products the package top surface mimics the bottom surface. Ultimately, when the package and the electronic device are the same size, such as in chip-scale packaging, the substrate camber requirement will be the same as the via bulge requirement, for example about 30 microns. This trend increases the need to improve the camber control on small and thin ceramic packages.
Several methods have been proposed to reduce camber in ceramic packages during sintering.
In U.S. Pat. No. 5,130,067 (Flaitz et al.) and U.S. Pat. No. 4,340,436 (Dubetsky et al.), the disclosures of which are incorporated herein by reference, the camber of a substrate is kept under control by the use of an externally applied force during all or part of the sintering process. The Flaitz process uses weights with openings which allow the sintering furnace gas to access the ceramic surface through the sinter cycle. The Dubetsky method processes the ceramic product in two steps: the first step is done without weights to allow gas access to the ceramic when needed, and the second step uses weights to carry the ceramic densification step. In both methods, the use of weights reduces the furnace capacity and increases the furnace thermal load; therefore, the sintering cost is increased when compared to the cost of sintering the same substrates without weights.
An alternative method to control camber on thin packages has been shown in U.S. Pat. Nos. 5,369,056 and 5,369,058 (Burns et al.). These patents describe a method to modify or prevent camber of thin packages by using layers with different coefficient of thermal expansion (CTE) on the package surface than the CTE of the package body. This approach is also practiced in ceramic packages when it is desirable to develop a compressive layer on the package surface to improve the ceramic surface mechanical properties. Unfortunately, the use of a CTE gradient is only practical when mechanical properties of the package are suitable for such effect, like plastic or metal assemblies with low elastic modules. Ceramic packages, which have high elastic modules, will not bend sufficiently when using the Burns methods to compensate for camber problems.
Ceramic package camber is produced during the sintering process by two independent mechanisms: ceramic shrinkage rate gradients in the package, and the difference in shrinkage rate between the ceramic and metal phases found in a typical electronic ceramic package. Both mechanisms must be controlled simultaneously to produce a substrate with low camber. The ceramic shrinkage rate gradient can be reduced by proper selection of the ceramic layer materials.
The use of specially shaped shims has also been described in the literature, such as, in IBM Technical Disclosure Bulletin, “
Method for Reduction of Shrinkage Distortion in Ceramic Substrates
”, Vol. 23, No. 5, Pages 1885-1886 (October 1980) (Brownlow) or U.S. Pat. No. 3,879,509 (Elderbaum) where efforts have been made to reduce ceramic shrinkage rate gradients during the lamination process.
U.S. Pat. No. 6,117,367 (Bezama et al.), the disclosure of which is incorporated herein by reference, discloses a set of pastes that reduce substrate defects, such as, via bulge and camber. The pastes are comprised of a metal having high conductivity, frit which includes glass, an organic binder, and a solvent, optionally with a surfactant.
Attempts to reduce the difference in shrinkage rate differential between the ceramic and the metal have not been successfull because of the intrinsic different nature of the materials being co-sintered.
However, it is possible to minimize the metal-i
Bezama Raschid J.
Bird Kenneth A.
Piciacchio Alan
Rita Robert A.
International Business Machines - Corporation
Jones Deborah
Pepper Margaret A.
Stein Stephen
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