Planar interconnect for integrated circuits

Details Planar interconnect for integrated circuits Planar interconnect for integrated circuits

1983-06-16

1986-10-14

Lusignan, Michael R.

Coating processes

Electrical product produced

Integrated circuit, printed circuit, or circuit board

156643, 156662, 357 50, 357 71, 427 86, 427 88, 427 96, 427259, B05D 306, B05D 512, B44C 122, G03C 1500

Patent

active

046171932

ABSTRACT:
An integrated circuit having a plurality of devices on a substrate is disclosed, wherein a plurality of metallization layers, separated by a plurality of insulating layers, are used to interconnect the devices. Each metallization layer is recessed in an upper portion of a corresponding dielectric layer. A metallization layer is connected to a lower one, or, in the case of the first metallization layer, to the devices, by solid contacts extending through via windows in the lower portion of the corresponding dielectric layer. A method of manufacturing such an integrated circuit is also disclosed, whereby each layer is formed in two steps. First, the lower portion of the insulating layer is deposited, the contact pattern opened and the vias windows filled with metal to provide contacts even with the top surface of the lower portion of the insulating layer. Then, the upper portion of the insulating layer is deposited over the lower portion, the metallization pattern opened, and the pattern filled with metal up to and even with the top surface of the upper portion of the insulating layer. The metal filling step is produced by depositing a metal layer over the corresponding portion of opened insulating layer, masking the opened regions and selectively and directionally removing the unprotected metal layer.

REFERENCES:
patent: 3985597 (1975-05-01), Zielinski
patent: 4367119 (1980-08-01), Logan et al.
patent: 4430153 (1984-02-01), Gleason et al.
patent: 4451326 (1984-05-01), Gwozdz
patent: 4457820 (1984-07-01), Bergeron et al.
patent: 4460435 (1984-07-01), Maa
patent: 4474642 (1984-10-01), Nakane et al.
patent: 4484979 (1984-11-01), Stocker
patent: 4489101 (1984-12-01), Shibata
L. B. Rothman, "Process for Forming Passivated Metal Interconnection System with a Planar Surface", J. Electrochemical Society: Solid-State Science and Technology, vol. 130, No. 5, May 1983.

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