Planar inductor with segmented conductive plane

Details Planar inductor with segmented conductive plane Planar inductor with segmented conductive plane

2000-12-19

2003-07-15

Pham, Long (Department: 2814)

Inductor devices

With electric and/or magnetic shielding means

C257S531000

Reexamination Certificate

active

06593838

ABSTRACT:

FIELD
The present invention pertains generally to integrated circuits. More particularly, the present invention relates to integrated circuits having high quality inductors with a segmented conductive plane.
BACKGROUND
Due to many considerations including cost, size and reliability, inductors have been fabricated on integrated circuits (ICs) instead of being external components which are coupled to the pins of the IC. The inductors typically have a spiral structure lying in a plane in a layer of the IC. For many applications, including radio frequency (RF) circuits, having planar inductors with a high Q (quality factor) is a significant requirement. The Q of an inductor is proportional to the magnetic energy stored in the inductor divided by the energy dissipated in the inductor in one oscillation cycle. The amount of magnetic energy stored in an inductor is directly proportional to the value of inductance of the inductor. The amount of energy dissipated in the inductor depends on resistive elements associated with the inductor.
Simply fabricating a spiral planar inductor on an IC does not result in a high Q device.
FIG. 1
illustrates a cross-section of a typical spiral inductor
12
formed on an integrated circuit
10
. The spiral inductor
12
is fabricated from a layer of metal formed during the integrated circuit fabrication process. The first end
14
of the spiral inductor
12
is generally connected to a circuit trace on the same layer of metal as the spiral inductor
12
. The second end
16
of the spiral inductor is generally connected through a via to another circuit trace which resides on another layer of metal. The layers of metal are separated by the insulating layer
18
.
FIG. 2
is an equivalent circuit depicting the spiral inductor
12
shown in
FIG. 1
together with its associated parasitic capacitance, resistance, and inductance.
As stated above, the amount of power dissipated in the resistive elements associated with the inductor adversely affects the Q of the inductor. The resistive elements R
s
, R
SUB
, shown in
FIG. 2
, dissipate power. R
SUB
represents the resistive substrate. A voltage between inductor
12
and substrate ground
22
creates an electric field across insulation layer
18
and substrate
20
. If the voltage varies, the resulting changing electric field will cause current to flow through substrate
20
. The current flow through the resistive substrate represented by R
SUB
dissipates power. The losses due to R
SUB
limit the Q of an inductor.
In an attempt to improve inductor performance, R. Merrill et al. in “Optimization of high Q integrated multi-level metal CMOS,” 1995 International Electron Devices Meeting and Santa Clara Valley Section 1996 Winter Half-Day Symposium, proposed placing a grounded shield or conductive plane between the inductor and the substrate.
FIG. 3
illustrates a spiral inductor
12
with a conductive plane
32
between inductor
12
and substrate
20
. The grounded conductive plane electrically isolates the inductor from the substrate and eliminates losses due to penetration of the inductor electric field into the substrate. However, the current flowing in the inductor generates eddy currents in the conductive plane which produce a magnetic field that opposes the magnetic field of the inductor, resulting in a reduced net magnetic field. The reduced net magnetic field reduces the effective inductance and limits the inductor Q. Thus, any gain in Q due to reducing or eliminating R
SUB
may be cancelled by the decrease in inductance due to the reduced net magnetic field.
To better control the flow of eddy currents in the conductive plane, Grzegorek et al. U.S. Pat. No. 5,760,456 proposed making the conductive plane out of plural segments which extend from the edges of the conductive plane towards the center of the planar inductive structure.
FIGS. 4
,
5
,
6
show three different types of modifications to conductive plane
32
in which the conductive plane is located between spiral inductor
12
and substrate
20
, and the conductive plane is segmented. To prevent the flow of eddy currents along the outer edges of the plane, a gap
94
is placed in one of the outer edges. The gap should be large because a small gap acts as a capacitor. At a certain frequency, the capacitor will act as a short circuit and an eddy current with flow along the perimeter of the conductive plane, resulting in a lower inductance. To have a large gap the conductive layer has to cover an area larger than the area covered by the spiral inductor. Allowing the conductive layer to cover a larger area prevents achievement of a relatively high density of devices on a chip. High densities permit economical production of reliable products among other benefits. Moreover, since the capacitance due to the gap cannot be completely eliminated, there will be a frequency beyond which the inductor has a low Q because eddy currents will flow.
As described above, existing solutions are not capable of providing the relatively high Q inductors required by many electronic circuits. Additionally, existing inductors and their corresponding conductive planes require a relatively large area of chip space. Consequently, it is desirable to provide the relatively high Q inductors required by many electronic circuits, and inductors that require a relatively small area of chip space.
SUMMARY
According to an embodiment of the invention, an integrated circuit inductor structure is described. The integrated circuit inductor structure has a substrate disposed below an inductor. The structure also has plural conductive segments located between the substrate and the inductor. The conductive segments connect at substantially a point below the center of the inductor. An insulating layer lies between the inductor and the conductive segments.


REFERENCES:
patent: 5760456 (1998-06-01), Grzegorek et al.
patent: 5959522 (1999-09-01), Andrews
patent: 6124624 (2000-09-01), Van Roosmalen et al.
patent: 6310386 (2001-10-01), Shenoy
patent: 6310387 (2001-10-01), Seefeldt et al.
patent: 0 780 853 (1997-06-01), None
patent: 356125866 (1981-10-01), None
patent: WO 98/50956 (1998-12-01), None
On-Chip Spiral Inductors with Patterned Ground Shield for Si-Based RF IC's. IEEE Journal of Solid State Circuits, vol. 33 (1998), pp. 743-752.
On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's. Symposium on VLSI Circuits Digest of Technical Papers (1997), pp. 85-86.
Spiral Inductor Substrate Loss Modeling in Silicon RFICs. Microwave Journal, Mar. 1999 pp. 66-81.

Affiliated with

Also associated with

Rating

Planar inductor with segmented conductive plane does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Planar inductor with segmented conductive plane, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Planar inductor with segmented conductive plane will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3047476