Planar HBT-FET Device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

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Details

257192, 257197, 257260, 257279, 257284, 257586, 257591, H01L 2972

Patent

active

052508269

ABSTRACT:
A III-V compound planar HBT-FET device integrates field effect transistors (FETs) with heterojunction bipolar transistors (HBTs) formed on the same semiconductor substrate. An HBT fabricated on the substrate includes a collector, a base, and an emitter. The HBT emitter comprises a lightly doped layer of a first conductivity type deposited atop a heavily doped base layer of a second conductivity type, a lightly doped emitter cap layer of the first conductivity type deposited atop the emitter layer, and a heavily doped emitter contact layer of the first conductivity type deposited atop the emitter cap layer. A FET, isolated from the HBT by areas of ion implantation, is formed in the layers of material deposited during fabrication of the HBT. The FET has a source and a drain formed in the heavily doped emitter contact layer, a gate recess etched in the emitter contact layer between the source and drain, and a Schottky gate metal contact deposited on the lightly doped emitter cap layer exposed in the gate recess. A back gate electrode can be deposited on the base layer to form a dual-gate FET comprising a front gate MESFET and a back gate junction FET. Connecting the back gate to an external power supply reduces backgating effects, provides radiation hardening, allows modulation of the back gate potential for tuning the threshold voltage of the FET, and provides for mixer-type applications with separate signals on the two gates.

REFERENCES:
patent: 4821090 (1989-04-01), Yokoyama
patent: 5027170 (1991-06-01), Nishiguchi et al.
patent: 5068756 (1991-11-01), Morris et al.
K. Itakura, Y. Shimamoto, T. Ueda, S. Katsu, and D. Ueda, "A GaAs Bi-FET Technology for Large Scale Integration," IEDM 89, pp. 389-392 (IEEE, 1989).

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