Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
2000-08-29
2002-04-23
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S637000
Reexamination Certificate
active
06376899
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the field of semiconductor fabrication. More specifically, the present invention relates to integrated circuits that include structures that reduce or prevent damages to the integrated circuit.
(2) Prior Art
FIG. 1
shows a cross-sectional view through a semiconductor wafer
100
. Semiconductor wafer
100
includes a silicon substrate
101
that has several dielectric layers
102
,
103
and
104
formed thereupon by processes that are well-known in the art. The figure also shows three metal layers that have been deposited, masked, and etched to form metal layers
105
,
106
, and
107
. Metal layers
105
-
107
overlie device regions to connect the various devices and the subsequently deposited metal layers. A top dielectric layer
111
(passivation layer) is then formed over the terminal metal layer
105
to planarize, insulate the electrical devices and interconnects, to prevent leakage of electrical current through the passivation layer, etc. The passivation layer
111
may include a hard passivation layer
113
typically made of silicon nitride (SiN) and a soft passivation layer typically made of polyamide
115
. The polyamide layer covers the Silicon/Nitride layer. The soft passivation layer is deposited by Plasma Enhanced Chemical Vapor Deposition or other typically known passivation layer deposition processes. The layer of silicon nitride is then covered by polyamide or another type of soft passivation layer.
FIG.
2
(
a
) illustrates a cross-section through the semiconductor wafer of
FIG. 1
where the soft passivation layer
115
is partly delaminated from the hard passivation layer
113
. The delamination typically causes moisture and other impurities to penetrate in the semiconductor wafer. One reason for the passivation layer's delamination is that the die is assembled into a plastic package which is more conducive to propagation of external forces within the package and to the die. The passivation layer may also delaminate when the die and the passivation layer are subjected to pressure pot testing (steam at a pressure greater than atmospheric pressure). One theory explaining this type of delamination is that steam dissolves or weakens the bonds within the passivation layer causing the passivation layer itself to delaminate.
Delamination is more likely to occur at the interface between the passivation layer
111
and the terminal metal layer
105
. Delamination typically starts at the edge of the die and propagates towards the center of the die. If the delamination reaches an electrical interconnect, the forces within the die that cause the delamination are applied to the electrical interconnect causing the electrical interconnect to rip apart at weak points thereof.
FIG.
2
(
b
) illustrates another cross section of the semiconductor wafer of
FIG. 1
where the polyamide layer
115
delaminates together with the silicon nitride layer
113
.
FIG.
2
(
c
) illustrates a cross section of the semiconductor wafer of
FIG. 1
where the terminal metal layer
105
and the passivation layer
111
, including the silicon nitride layer
113
and the polyamide layer
115
, delaminate from dielectric layer
104
as a result of external forces applied to the semiconductor wafer of FIG.
1
.
In certain integrated circuits, the TML includes a continuous guard ring that surrounds a die active area of the integrated circuit. The guard ring protects the die active area from damages. Damages, among other things, include invasion by foreign impurities, such as sodium and magnesium, that exist in the environment, and certain mechanical damages, including micro-cracks that may be produced when a wafer is cut into dices. Micro-cracks propagate to die active areas of the chips producing damages thereto.
FIG. 3
illustrates a top view of a die
300
that has a guard ring
304
surrounding the die active area
301
of the integrated circuit. Guard ring
304
protects the die active area from damages.
Present state of the art guard rings are not robust enough to withstand the various forces exerted to the IC. The guard rings may get broken during reliability testing, specifically during temperature cycling to which the integrated circuit is subjected. Shear forces may be exerted to the guard ring during temperature cycling causing damages particularly at and near the corners of the guard ring where these forces have a more destructive effect.
FIG. 4
illustrates a cross-sectional view through a part of a guard wall including guard ring
404
formed in a terminal metal layer (TML) (Metal
5
). A passivation layer including a conformal nitride layer
406
is formed over the TML including guard ring
404
. The nitride layer
406
formed over guard ring
404
has a re-entrant wall
410
that forms a re-entrant angle
408
with a surface
412
of the layer of nitride deposited over the terminal layer of interlayer dielectric (ILD
4
)
416
. The Metal
5
guard ring
404
is coupled to a Metal
4
guard ring, by way of via
418
. During temperature cycling, guard ring
404
tends to move sideways due to the expansion and contraction of the metal of which the guard ring is made and to the shear forces
419
exerted upon the re-entrant wall
410
. Moreover, due to forces
419
exerted upon re-entrant wall and the fact that the portion of nitride in the vicinity of the re-entrant angle
408
is thinner, moisture may penetrate into the corner defined by re-entrant angle
408
, causing the nitride to crack. This may cause exposure of the Metal
5
guard ring
404
to outside agents that may damage the Metal
5
guard ring
404
.
The fact that the Metal
5
guard ring
404
protrudes outside causing the nitride layer to have the profile shown in
FIG. 4
(with the re-entrant wall
410
and re-entrant angle
408
) causes problems at the interface between the Metal
5
and the terminal dielectric layer
416
. Moreover, guard ring
404
contributes to instability in the guard wall including guard ring
404
and the other layers of metal as guard ring
406
is subjected to high forces (shear forces). It is desirable to provide a guard wall that is stable and does not contribute to the type of damages caused to the nitride layer and to the guard wall explained above.
SUMMARY OF THE INVENTION
The present invention provides an integrated circuit that includes a substrate and at least one dielectric layer and a metal layer formed upon the substrate. The at least one dielectric layer includes a terminal dielectric layer. The integrated circuit further includes a planar passivating layer formed upon the terminal dielectric layer.
REFERENCES:
patent: 4841354 (1989-06-01), Inaba
patent: 5270256 (1993-12-01), Bost et al.
patent: 5300461 (1994-04-01), Ting
patent: 5306945 (1994-04-01), Drummond
patent: 5612254 (1997-03-01), Mu et al.
patent: 5675187 (1997-10-01), Numata eet al.
patent: 5739579 (1998-04-01), Chiang et al.
patent: 5789302 (1998-08-01), Mitwalky et al.
patent: 5831330 (1998-11-01), Chang
patent: 5834829 (1998-11-01), Dinkel et al.
patent: 5977639 (1999-11-01), Seshan et al.
Mielke Neal R.
Seshan Krishna
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Potter Roy
LandOfFree
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