Planar gate turn-off field controlled thyristors and planar junc

Details Planar gate turn-off field controlled thyristors and planar junc Planar gate turn-off field controlled thyristors and planar junc

1984-07-11

1986-02-11

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 148175, 148DIG50, H01L 29747

Patent

active

045691185

ABSTRACT:
Gate turn-off field controlled thyristors having high forward blocking capabilities and high blocking gains, and planar, junction gate field effect transistors having high source-to-drain breakdown voltage capability with high differential blocking gain, include a gate region having a plurality of vertical-walled grooves. The devices are fabricated by preferentially etching one surface of a semiconductor substrate, selectively refilling the grooves with a vapor phase epitaxial growth, forming a plurality of first electrode regions on the same surface and interdigitated with the gate region, and forming a second electrode region on the opposite surface of the substrate.

REFERENCES:
patent: 3322581 (1967-05-01), Hendrickson et al.
patent: 3762966 (1973-10-01), Engeler et al.
patent: 3855608 (1974-12-01), George et al.
patent: 3953879 (1976-04-01), O'Connor-d'Arlach et al.
patent: 3969746 (1976-07-01), Kendall et al.
patent: 4037245 (1977-07-01), Ferro
patent: 4181542 (1980-01-01), Yoshida et al.

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