Planar encapsulation process

Details Planar encapsulation process Planar encapsulation process

1995-11-17

1997-01-21

Picard, Leo P.

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

174 522, 257702, 257706, 257713, H01L 2302, H01L 2328, H01L 2314, H01L 2310

Patent

active

055961720

ABSTRACT:
A method for encapsulating a surface of an integrated circuit to protect the surface. The surface has an outer peripheral area and an inner area to be encapsulated. A frame is provided for handling an integrated circuit package. A plurality of leads are coupled between the frame and the outer peripheral area. An encapsulation material is dispensed on the outer peripheral area covering and protecting a portion of the leads and integrated circuit. A planar encapsulation material is deposited for covering and protecting the inner area. The planar encapsulation material provides a planar surface.

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patent: 5233130 (1993-08-01), Nishino
patent: 5422383 (1995-06-01), Takahashi
patent: 5426330 (1995-06-01), Joshi

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