Planar dielectric isolated wafer

Details Planar dielectric isolated wafer Planar dielectric isolated wafer

1991-05-24

1992-05-19

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437228, 437233, H01L 2176

Patent

active

051148757

ABSTRACT:
A substantially planar dielectric wafer is formed by utilizing a polysilicon filler to remove surface irregularities (15, 15'). The polysilicon filler is formed by filling surface irregularities (15, 15') with polysilicon (19) and polishing the polysilicon (19) to form a substantially planar surface. A polishing stop (18) terminates the polishing and prevents damage to the wafer's isolated tubs (13). The polishing stop (18) can also be used as a mask during field oxide growth. The polysilicon filler also protects underlying areas (12) from subsequent etch operations. During subsequent field oxide growth, polysilicon layer (19) is converted to silicon dioxide which enhances dielectric isolation of each tub (13).

REFERENCES:
patent: 3571919 (1971-03-01), Gleim et al.
patent: 4870029 (1989-09-01), Easter et al.

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