Placement of components on circuit substrates

Details Placement of components on circuit substrates Placement of components on circuit substrates

1983-09-12

1986-03-18

Krass, Errol A.

Boots, shoes, and leggings

364488, 364490, G06F 1546

Patent

active

045772762

ABSTRACT:
In laying out integrated circuits on a substrate, the placement of the components relative to each other is important in minimizing conductor area and hence chip area. Large scale integration often uses polycells which are lined up in rows to realize the digital logic circuitry. A partitioning procedure is disclosed which iteratively separates the cells into maximally connected subcells, eventually to assign them to rows so as to minimize conductor area. A technique called terminal propagation takes into account at every iteration the location of connections outside of the partitioned area. Rectilinear Steiner trees are generated to aid in terminal propagation.

REFERENCES:
patent: 3617714 (1971-11-01), Kernighan et al.
"Producing Integrated Circuits from a Circuit Logic Input" by Bilous et al., IBM Technical Disclosure Bulletin, vol. 13, No. 5, Oct. 1970, pp. 1084-1089.
"PRO--An Automatic String Placement Program for Polycell Layout", Proceedings of the 13th Design Automation Workshop, 1976, G. Persky, pp. 417-424.
"A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation", Proceedings of the 16th Design Automation Workshop, Jun. 1979, U. Lauther, pp. 1-10.
"An Iterative Algorithm for Placement and Assignment of Integrated Circuits", Proceedings of the 12th Design Automation Workshop, 1975, D. C. Schmidt and L. E. Druffel, pp. 361-368.
"A Placement Capability Based on Partitioning", Proceedings of the 16th Design Automation Workshop, 1979, L. I. Corrigan pp. 406-413.
"Min-Cut Placement", J. Design Automation & Fault Tolerant Computing 1(4), Oct. 1977, M. A. Breuer, pp. 343-362.
"A Proper Model for the Partitioning of Electrical Circuits", Proceedings of the 9th Design Automation Workshop, 1972, D. G. Schweikert and B. W. Kernighan, pp. 57-62.
"An Efficient Heuristic Procedure for Partitioning Graphs", Bell System Technical Journal 49(2), 1970, B. W. Kernighan and S. Lin, pp. 291-308.
"Net Wiring for Large Scale Integrated Circuits", IBM Technical Report RC 1375, Feb. 1965, M. Hanan, pp. 1-17.
"A Linear-Time Heuristic for Improving Network Partitions", Proceedings of the 19th Design Automation Workshop, 1982, C. M. Fiduccia and R. M. Mattheyses, pp. 175-181.

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