Placement of an integrated circuit

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...

Reexamination Certificate

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Details

C438S106000, C438S125000, C438S129000, C257SE21499, C257SE21511, C257SE21705

Reexamination Certificate

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07851255

ABSTRACT:
Disclosed herein is a method of positioning and placing an integrated circuit on a printed circuit board. The integrated circuit comprises first geometrical elements. The first geometrical elements are of one or more predefined shapes and are located on one or more predefined surfaces of the integrated circuit. The printed circuit board comprises second geometrical elements. The second geometrical elements are shaped to accommodate the first geometrical elements. The first geometrical elements are designed to fit into the second geometrical elements. The first geometrical elements are positioned and placed over the second geometrical elements. The first geometrical elements come in contact with the second geometrical elements at two or more points. The positioning and placement of the first geometrical elements over the second geometrical elements limits displacement of connections of the integrated circuit from the printed circuit board.

REFERENCES:
patent: 2001/0016435 (2001-08-01), Fujimura
patent: 2003/0111727 (2003-06-01), Kurusu
patent: 2004/0169275 (2004-09-01), Danvir et al.
patent: 2006/0118971 (2006-06-01), Gracias
patent: 58121654 (1983-07-01), None
patent: 62018722 (1987-01-01), None

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