Place and route method for integrated circuit design

Details Place and route method for integrated circuit design Place and route method for integrated circuit design

1999-06-14

2001-03-27

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

With electrical circuit layout

C438S129000

Reexamination Certificate

active

06207479

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for integrated circuit design, and more specifically, to a method of using a checkerboard pattern to constrain interlayer connection points (contact/via) and a connection cell placed in a via during automatic place and route.
BACKGROUND OF THE INVENTION
As the technology scales to small dimensions, one of the most difficult obstacles to continued scaling is the level to level alignment in lithography, especially in complex structures of metals and contacts. Consequently, the level of contact from one to another for nesting tolerance or for borders used around contacts and the design rule thereof become crucial limitations for densely packed chip.
Most ASICs (application specific integrated circuits), such as microprocessor, graphic-used chip, have a bit less repetition on the transistors than the memory-type integrated circuit. Hence, for approaching the goal of high packed density in a ASIC IC chip suffers a more strict challenge than memory IC chip.
Recently, there are many conventional layout tools have been developed for the microelectronic devices in a ASIC IC chip. For examples, one is the gate array methods, which are best suited to quick, turnaround random logic functions, the other is standard cell system, which improve on the utilization of silicon and range of function available to the designer. In addition, the symbolic layout, such as fixed grid layout, gate matrix layout, or virtual grid symbolic layout, are developed to simplify the complicated layout tasks. No matter what approaches are taken, the final stage of metal wires' layout are still using the grid design rule since it can obtain the highest packed density on a chip as far as currently technology is concerned. The grid layout indicated the metal wires in the same floor are uniform ud and parallel each other, say at a X direction. The next floor of metal wires are placed the same or all in a Y direction. The column metal wires and the row metal wires intersect to construct the grids. Each of the corners of the grids is a potential site for forming a contact/via so as to interconnect the metal wires on each floor.
There are some technology terms and labels presented in this application will be defined here as follows:
1. minimum via size “A” : indicated that the via will be failed because the misalignment of etching or/and lithographic technologies, or the ineffective deposited the metal into the via while the via size is smaller than this value.
2. minimum line extended length “B”: indicated a minimum metal wire length, which is measured from a edge of a via to the end of metal wire.
3. minimum line-end spacing “C”: is a minimum spacing between two end terminals of two metal lines which are lined up each other.
4. minimum metal wire island “D” : indicated a minimum length defined during layout or it would be failed due to the lithography or the etch process.
5. minimum spacing of metal wires “E”: indicated a minimum average spacing between two adjoining and parallel metal wires.
6. minimum width of a metal wire “W”: indicated a minimum average width to prevent the discontinuous of the metal wires due to the issues of the topography of structure or step coverage during the wire deposition.
7. grid size G1,G2 or G, wherein G1 or G2 is a size of a grid constructed by column wire and row wire using a conventional method. The grid size represents the minimum feature or placement tolerance that is desired in a given process.
8. pitch “P”; a sum of minimum width of a metal wire and minimum spacing of two adjoining metal wires.
From the forgoing depicted, it is realize that the short or discontinuous of the wires results from the process degradation, such as lithography, etching and deposition, needs to avoid. Furthermore, some electrical performance characteristics such as the electromigration, reliability, power dissipation, transfer delay, and noise isolation, will need to take into account while setting the design rule for layout the wires is done so as to obtain the best possible compromise between performance and yield. In general, the worse condition is set,
FIG. 1
shows an example of synoptic layout the metal wires. The metal wires
20
on the upper floor are uniform spaced and parallel each other (along Y direction), the same is the metal wires
30
(but along X direction)on the lower floor. The column metal wires
20
and the row metal wires
30
intersect so that the grids are formed. In the figure, the small circle and square are respectively, the potential site for a via position and a real via defined therein to connect the metal wires
20
and
30
of two floors.
Still referring to
FIG. 1
, as aforementioned issues discussed, it is found that that to obtain the best possible compromise between performance and yield, the grid size G1 needs to be larger than the sum of A+2×b+C, or grid size G2 needs to be larger than the sum of 0.5×D+C, where the labels “A”, “B”, “C” and “D” are defined as above. In accordance with the conventional method, the grid size is a larger value chosen from G1 and G2.
Table 1 lists some of relative parameters for 0.25 &mgr;m and 0.18 &mgr;m feature sizes of the process.
TABLE 1
Feature size of process
0.25 &mgr;m
0.18 &mgr;m
Via size A &mgr;m
0.36
0.26
Min. line extended length B &mgr;m
0.09
0.06
Min. line-end spacing C &mgr;m
0.40
0.28
Min. metal wire island D &mgr;m
0.90
0.72
Grid size G1
0.94
0.66
Grid size G2
0.85
0.64
Although above design rule is satisfied for some cases especially for the number of vias is larger, however the design rule set forth in above isn't efficient for the number of the vias not dense. It is because the grid size can't be reduced. The present invention provides a method to resolve above issues.
SUMMARY OF THE INVENTION
An object of the invention provides a metal-wire layout method so that the grid size can be equal to minimum metal pitch, and thus the chip size is reduced.
An another object of the invention is to improve the electromigration reliability.
The present invention provides a method of placing and routing metal wires for integrated circuit. The method comprises of following: at first, a grid pattern is constructed by a plurality of floors with metal wires therein. The metal wires are uniform spaced and parallel each other in each floor. Furthermore, the metal wires in at least one floor are perpendicular to the metals wires in others floor so as to fully utilize the available space in a chip, and to form a set of grids. The grid size is set to be equal to the minimum width of metal wire plus the minimum spacing of two adjoining metal wires. However, each via placed in the grid pattern has to be constrained by a checkerboard-like pattern. The checkerboard-like pattern consists of potential via sites and forbidden sites, wherein the potential via sites and said forbidden sites are intervened each other so that each potential via site in a comer of the grid has forbidden sites at its nearest neighbor comers. Furthermore, the connection cells is constructed and placed in a defined via for connecting the metal wires in individually floor.


REFERENCES:
patent: 5088061 (1992-02-01), Golnabi et al.
patent: 5629860 (1997-05-01), Jones et al.
patent: 5872027 (1999-02-01), Mizuno

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