PLA-Based finite state machine with two-level control timing and

Details PLA-Based finite state machine with two-level control timing and PLA-Based finite state machine with two-level control timing and

1982-12-08

1984-12-11

Zache, Raulfe B.

Boots, shoes, and leggings

364716, 307465, 34082583, G06F 922

Patent

active

044882297

ABSTRACT:
A PLA (e.g., 100) operates with two-level clock control timing, that is, with a pair of master and slave registers (e.g., 12 and 13) connected to the PLA wordlines (e.g., W.sub.1, W.sub.2, . . . W.sub.n) between the PLA's AND and OR planes (e.g., 11 and 14). The slave register's output to the OR plane is controlled by a combinational logic device (e.g., 21), such as an AND gate to which a WAIT signal is applied. In this way, when the WAIT signal (e.g., W) is available at the beginning of a given cycle of the clock control timing, the output of the PLA (including PLA feedback) can respond to this WAIT signal before the end of the given cycle--that is, the PLA is capable of same-cycle decision making.

REFERENCES:
patent: 3593289 (1971-07-01), Lerch et al.
patent: 3974366 (1976-08-01), Hebenstreit
patent: 4032894 (1977-06-01), Williams
patent: 4034356 (1977-07-01), Howley et al.
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4399516 (1983-08-01), Blahut et al.
patent: 4409499 (1983-10-01), Zapisek et al.
patent: 4415818 (1983-11-01), Ogawa et al.
patent: 4429238 (1984-01-01), Harrison
E. Hebenstreit et al., "High-Speed Programmable Logic Arrays in ESFI SOS Technology," IEEE Journal of Solid-State Circuits, vol. SC-11, No. 3, Jun. 1976, pp. 370-374, (FIG. 3).
C. Mead et al., Introduction to VLSI Systems, 1980, pp. 75-84.
"PLA Test Enhancement", by Logue et al., IBM Tech. Discl. Bull., vol. 23, No. 3, Aug. 1980, pp. 1116-1117.
"PLA Else Clause Implementation" by Kraft et al., IBM Tech. Discl. Bull., vol. 25, No. 12, May 1983, p. 6502.
"Clocked PLA w/Dummy Circuit Forming Clock Pulse for Inter-Array Driver w/Worst-Case Delay" by Kluga, IBM T.D.B., vol. 24, No. 6, Nov. 1981.
"Programmable Logic Array Decoding Technique" by Howley et al., IBM Tech. Discl. Bull., vol. 17, No. 10, Mar. 1975, p. 2988.

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