Pixel memory arrangement for information display system

Details Pixel memory arrangement for information display system Pixel memory arrangement for information display system

1988-01-05

1990-08-21

Brier, Jeffery A.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340798, G09G 102

Patent

active

049510428

ABSTRACT:
A pixel data memory is provided for use with an information display system having a raster scan screen divided into a plurality of pixels each of which represents a separate area of the screen. The memory comprises a multiple-bit memory plane (13) capable of providing a plurality of separate bit locations each of which may correspond to a separate display pixel and arranged to store pixel data in the form of a plurality of multiple-bit words. The memory plane (13) comprises a number of memory chips each capable of storing a separate bit of each of the multiple-bit words. An address generator (10) is operable to generate the addresses of required individual bit locations in the memory plane. A number of separate control circuits (14) are provided, equal to the number of bits in each word. Each control circuit (14) is associated with a separate memory chip and is responsive to a generated address defining a bit location on that chip to access the pixel data identified by the bit at that location. The control circuits are operable in an asynchronous manner so as to allow pixel data to be written into a read out from a number of bit locations simultaneously.

REFERENCES:
patent: 4092728 (1978-05-01), Baltzer
patent: 4742474 (1988-05-01), Knierim
patent: 4745407 (1988-05-01), Costello
patent: 4766431 (1988-08-01), Kobayashi et al.

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