Pixel clock PLL frequency and phase optimization in sampling...

Details Pixel clock PLL frequency and phase optimization in sampling... Pixel clock PLL frequency and phase optimization in sampling...

2005-08-23

2005-08-23

Osorio, Ricardo (Department: 2673)

Computer graphics processing and selective visual display system

Display driving control circuitry

Display power source

C345S611000, C345S643000, C348S536000

Reexamination Certificate

active

06933937

ABSTRACT:
Pixel clock frequency and optimum sampling phase adjustment is an important requirement in Flat panel display monitors (FPDM) with an analog video interface. This invention proposes a new and more advanced method for frequency an optimum sampling phase determination. It is based on analyzing the content of the image to arrive at an optimum value of phase and frequency by directly optimizing image quality. The method differs from exsisting methods on two counts. First, no assumptions are needed about the precise value of expected frequency. Second, instead of following a two step approach of first determining frequency and then phase, this invention makes possible a single pass phase-frequency optimization.

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