Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
1999-09-15
2003-10-14
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S611000, C348S536000, C348S537000
Reexamination Certificate
active
06633288
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to providing images on a display and more particularly to providing and optimizing an image displayed from video signals.
BACKGROUND OF THE INVENTION
Pixel clock frequency and optimum sampling phase adjustment is an important requirement in flat panel display monitors (FPDM) with an analog video interface. This invention proposes a new and more advanced method for frequency and optimum sampling phase determination. It is based on analyzing the content of the image to arrive at an optimum value of phase and frequency by directly optimizing image quality. The method differs from existing methods on two counts. First, no assumptions are needed about the precise value of expected frequency. Second, instead of following a two step approach of first determining frequency and then phase, this invention makes possible a single pass phase-frequency optimization.
Transfer of pixels, lines and frames from the PC to the monitor follows a predefined and synchronous timing format. Besides the active data transfer period, inactive regions are required on top, bottom, left and right of a frame. In CRT monitors this time is allocated for retrace of the electron beam from end of one line to the beginning of the next line, or from end of a frame to beginning of the next frame. In LCD monitors, various housekeeping functions are performed by the drive electronics during the inactive region.
FIG. 1
shows the timing relationships between pixels, lines and frames. The Pixel Clock controls the basic pixel transmission rate. HSYNC is the horizontal synchronization frequency and marks the beginning of each line. Similarly VSYNC is used for vertical synchronization and marks the beginning of each frame. Data Enable (DE) is valid for the active period during which pixel data is transmitted.
Standard analog video interface between the PC and the monitor consists of the three RGB signals as well as horizontal and vertical synchronization signals. In Flat panel displays where the analog RGB video signals have to be converted into a digital format, it is important to sample the incoming signal at the pixel clock rate at an optimum sampling phase.
An example of vertical pin-stripe image highlights the importance of frequency and phase optimization.
FIG. 2
shows the relationship between incoming video data and sampling clock phase and frequency. For a vertical pinstripe image, alternating dark and bright pixels constitute the data signals. Due to channel bandwidth limitations, the data signals have a finite risetime. If the frequency of sampling is different from the pixel clock, the sampled data points do not correspond to actual pixel data. Consequently, vertical bands appear on the screen due to aliasing in the frequency domain. In addition, the active width of the image is modified. If the frequency but sampling phase is not optimum, differences in values of two consecutive pixels becomes small leading to poor contrast in the image. Determining the correct pixel clock frequency and finding the optimum sampling phase are crucial to obtain high quality images.
Existing Methods
The first generation flat panel monitors used On-screen display (OSD) based manual control to determine these parameters. Later, multi-synching techniques were developed where pixel clock frequency was deduced from the horizontal (HSYNC) and vertical (VSYNC) synchronization signal timings using table-based comparisons. Current monitors incorporate further refinements in pixel clock frequency determination by taking number of pixels between the borders of the image being displayed into account. Some degree of automation has been achieved in sampling phase adjustment as well based on techniques ranging from “centering” of the sampling frequency to “contrast maximization”. Following is a brief description of existing techniques for frequency determination and phase optimization.
Manual Adjustment
In this case the phase and frequency are varied the correct value of phase and frequency which optimize image quality and/or size.
Size Adjustment
In size based adjustment, the horizontal size of the active area of the image (calculated in number of pixels) is deducted. The actual size is measured between the left edge of the active image and right edge of the active image. The frequency is adjusted until the actual size is within one pixel of the expected size. Subsequently phase is adjusted such that the actual and expected sizes are identical.
Table Based Techniques
In this method, the frequency and polarity of HSYNC and VSYNC signals is measured. A table maps these parameters to the pixel clock frequency.
Contrast Maximization
This method is used for sampling phase optimization. In this method, the absolute difference between two neighboring pixels is monitored as a function of sampling phase. The optimum value of phase is the highest value of the difference and corresponds to maximum contrast in the image.
Limitations of Existing Methods
Existing methods have several limitations, which have an impact on the quality of adjustment procedure as well as time taken to adjust pixel phase and frequency. Manual Adjustment is reliable and can be used to adjust most images. However, it is extremely cumbersome and tedious and besides taking a long time, it requires the user to be very familiar and skilled with the adjustment procedure. Size Adjustment which is the existing method of automatic adjustment lead to accurate frequency for images which have a standard horizontal size and/or deducing the expected value of horizontal size is simple. Moreover, the method requires the images to have well defined borders at left and right edges. This leads to several situations where size based adjustment procedures fail to yield best results. Table based frequency adjustment works only for know video modes which are included in the table and fail whenever the video timings are non-standard. Contrast optimization works under the assumption that the value of frequency has been determined correctly.
Accordingly, what is needed is a system and method that overcomes the above-identified problems. The present invention addresses such a need.
SUMMARY OF THE INVENTION
Pixel clock frequency and optimum sampling phase adjustment is an important requirement in Flat panel display monitors (FPDM) with an analog video interface. This invention proposes a new and more advanced method for frequency and optimum sampling phase determination. It is based on analyzing the content of the image to arrive at an optimum value of phase and frequency by directly optimizing image quality. The method differs from existing methods on two counts. First, no assumptions are needed about the precise value of expected frequency. Second, instead of following a two step approach of first determining frequency and then phase, this invention makes possible a single pass phase-frequency optimization.
REFERENCES:
patent: 4905085 (1990-02-01), Faulhaber
patent: 5256875 (1993-10-01), Hoekman et al.
patent: 5321750 (1994-06-01), Nadan
patent: 5767916 (1998-06-01), West
patent: 5805233 (1998-09-01), West
patent: 5835155 (1998-11-01), Jennes et al.
patent: 5847701 (1998-12-01), Eglit
patent: 6011538 (2000-01-01), Eglit
patent: 6097444 (2000-08-01), Nakano
patent: 6147668 (2000-11-01), Eglit
patent: 6166775 (2000-12-01), Fukuda
Agarwal Sandeep
Johary Arun
Beyer Weaver & Thomas LLP
Osorio Ricardo
Sage, Inc.
Shalwala Bipin
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