Computer graphics processing and selective visual display system – Display driving control circuitry – Controlling the condition of display elements
Reexamination Certificate
1999-06-04
2002-05-28
Sax, Steven (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Controlling the condition of display elements
C345S215000
Reexamination Certificate
active
06396486
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a pixel clock generator, and more particularly, to a pixel clock generator for automatically adjusting the horizontal resolution of an OSD screen to meet the multi-sync requirement for the display.
2. Description of the Prior Art
A display is an important computer peripheral device that converts image signals into display images for display on the screen. This permits the use of data generated in the computer. The On-Screen Display (OSD) has become a fundamental control unit of the display as it can be used to directly adjust various display parameters such as color, contrast, or brightness. An OSD screen is composed of vertical synchronous signals. Each vertical synchronous signal comprises a plurality of horizontal synchronous signals forming horizontal scanning lines. Each of the horizontal synchronous signals comprises a plurality of pixel clocks to form the pixels of a horizontal scanning line. A high number of pixel clocks indicates denser sampling of the horizontal image signal and therefore a higher horizontal resolution, whereas a smaller number of pixel clocks indicates sparse sampling of the horizontal image signal and therefore a lower horizontal resolution. If the prior art display with OSD is in a different mode, i.e. with different vertical synchronous signals and different horizontal synchronous signals, the horizontal resolution value and the initial point of the horizontal position have to be adjusted so as to set the OSD screen.
Please refer to FIG.
1
and FIG.
2
.
FIG. 1
is a functional block diagram of a pixel clock generator according to the prior art.
FIG. 2
is a schematic timing diagram of the pixel clock generator
20
shown in
FIG. 1. A
pixel clock
18
is generated by a pixel clock generator
20
for sampling on a horizontal synchronous signal
14
. Once the initial point of the horizontal position of an OSD screen is set, the OSD horizontal image signal
16
may be displayed on the screen from the initial point. The pixel clock generator
20
of the prior art uses a phase locked loop circuit
22
to generate a proper pixel clock
18
. The phase locked loop circuit
22
comprises a control port
24
for receiving a multiplier N, an input port
26
for inputting a horizontal synchronous signal
14
, and an output port
28
for generating a pixel clock
18
. Multiplier N is the present resolution value. When stabilized, the phase locked loop circuit
22
generates pixel clocks
18
within the time period each of the horizontal synchronous signals is received with the number of pixel clocks
18
generated being a multiple of N (as shown in
FIG. 2
) . The frequency of the output port
28
of the phase locked loop circuit
22
is approximately equal to N times that of the horizontal synchronous signal
14
of the input port
26
. As shown in
FIG. 2
, the horizontal synchronous signal
14
comprises signals at two levels: high and low. The high level retrace signal denotes the required retracing time of the electron gun and the low level scan signal denotes the required scanning time of the electron gun. In other words, the horizontal scanning lines of the whole screen are generated within the time period of the scan signal of the horizontal synchronous signal
14
so the horizontal resolution of the actual image is determined only by the pixel clocks within the time period of the scan signal. So, according to the prior art method of sampling, the horizontal resolution and the initial position of the OSD screen have to be adjusted when in different modes. The present invention provides a simple method for automatic adjustment. The horizontal resolution and the horizontal initial position need not be adjusted.
Please refer to FIG.
3
.
FIG. 3
is a schematic diagram of the time sequence of the retrace signals of the horizontal synchronous signals
14
and the scan signals shown in FIG.
2
. In
FIG. 3
, t
1
denotes the time required to retrace the electron gun in the horizontal synchronous signal, t
2
denotes the scanning time required by the electron gun, and t
1
+t
2
denotes the time for inputting each horizontal synchronous signal
14
. Each horizontal synchronous signal can be considered to be composed of a retrace signal
15
and a scan signal
17
. When the pixel clock
18
remains unchanged, i.e. the horizontal resolution (N) of the image screen is fixed, and if the retrace time of the horizontal synchronous signal
14
changes from t
1
to t
1i
; the initial point of the displaying position of the OSD screen on the displaying screen will change from point a to point a+b. That is to say, the OSD screen on the displaying screen will change i.e. the proportion of horizontal synchronous signals taken up by the retrace time will effect the real resolution. If changing the resolution of the display, the retrace signal time of the electron gun will change and the necessary scanning time of the electron gun needed will also change. Since their ratio will not be the same, the initial position of the OSD screen on the display will change.
If the horizontal resolution is N, it is necessary to take N samples within the time period t
2
. If the horizontal resolution is changed to N+M, it is then necessary to take N+M samples within the time period t
2
. However, in the actual application, the prior art sampling method takes N samples within the time period t
1
+t
2
, and when the horizontal resolution is changed to N+M, it takes N+M samples within the time period t
1
+t
2
. So the prior art method causes the initial position of the OSD screen to change along with the change of the horizontal resolution. If the user changes mode (i.e. the horizontal resolution changes) the OSD screen often moves causing inconvenience.
To solve this problem, a Look-Up Table is created in software and the displaying position of the OSD screen is adjusted according to the resolution in conjugation with the Look-Up Table so that the OSD screen does not change with different resolutions. This prior art method of adjusting the OSD screen is very troublesome because the Look-Up Table has to be altered to fit new displaying devices with many adjusting procedures.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a pixel clock generator for automatically adjusting the horizontal resolution of an OSD screen to solve the above mentioned problem in using hardware.
In a preferred embodiment, the present invention provides a pixel clock generator for controlling the resolution of horizontal image signals of a displaying device, the displaying device comprising a screen and a display control circuit for displaying an image frame on the screen according to an incoming image frame signal, each image frame comprising a plurality of horizontal image lines, the image frame signal comprising a plurality of horizontal synchronous signals and horizontal image signals, each of the horizontal image signals being used for forming one of the horizontal image lines of the image frame, each of the horizontal synchronous signals comprising a scan signal and a retrace signal, the scan signal being used for directing the display control circuit to convert one correspondent horizontal image signal into a horizontal image line on the screen, and the retrace signal being used for directing the display control circuit to prepare for displaying another horizontal image line, the pixel clock generator comprising:
a phase locked loop (PLL) circuit having an input port for receiving the horizontal synchronous signals and a control port for receiving a multiplier wherein the PLL circuit generates a quantity of the pixel clocks approximately equal to the multiplier within the receiving time period of each of the horizontal synchronous signals; and
an adjusting circuit having three input ports for receiving a horizontal resolution value, the horizontal synchronous signals, and the pixel clocks generated by the PLL circuit wherein the adj
Hsiao Fu-Yuan
Kuo Shih-Tsung
Sax Steven
Weltrend Semiconductor Inc.
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