Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2007-08-08
2010-11-09
Osorio, Ricardo L (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S080000
Reexamination Certificate
active
07830342
ABSTRACT:
A pixel circuit is disclosed. The pixel circuit includes, at least a drive transistor; an input transistor; a first switching transistor; a second switching transistor; a retention capacity; and an electro-optic device. The retention capacity is connected, at both ends, to a gate node and a source node, respectively, of the drive transistor. The electro-optic device has rectification properties, and is determined in intensity by a value of a drive current coming from the drive transistor whose source node is connected to an anode thereof. The input transistor is connected, at one current end, to the gate node of the drive transistor, and samples a video signal to the retention capacity during a predetermined sampling period. The first switching transistor is turned on before the sampling period, and connects the gate node of the drive transistor at a predetermined reference voltage.
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Asano Mitsuru
Jinta Seiichiro
Mutsukura Takahiko
Tomida Masatsugu
Osorio Ricardo L
Rader & Fishman & Grauer, PLLC
Sony Corporation
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