Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-11-18
2001-07-17
Liang, Regina (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000
Reexamination Certificate
active
06262703
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to liquid crystal displays and more particularly to a liquid crystal display capable of storing video data.
DESCRIPTION OF THE RELATED ART
Liquid crystal displays (LCDs) have become a popular form of electronic displays. LCDs are composed of liquid crystals which are positioned between two pieces of glass. The crystals can be aligned such that in a normal state, light easily propagates through the liquid crystals. However, when an electrical field is present, the liquid crystals alter their alignment, greatly reducing the amount of light passing through the crystals. By applying an electrical field at different “pixels” or discrete regions on the LCD, an image can be formed on the LCD. An LCD can have more than 1,228,800 pixels. The resolution of the LCD is directly related to the density of pixels in the LCD array.
There are a number of alternative types of liquid crystals utilized commercially in LCDs. A first major type is referred to as twisted nematic liquid crystals. LCDs with twisted nematic liquid crystals produce pictures with high contrast. However, LCDs with twisted nematic liquid crystals have relatively narrow viewing angles, as well as slow molecular rotation times. A second type of liquid crystals is referred to as ferroelectric liquid crystals. LCDs with ferroelectric liquid crystals have wider viewing angles, because of their small cell gaps of 1 to 2 microns. In addition, ferroelectric liquid crystal displays (FLCDs) have a faster molecular rotation speed, typically in the range of 50 to 100 micro seconds.
A typical FLCD includes a display chip covered with a structure containing the ferroelectric liquid crystals, an illuminator, and viewing optics. Operation of a conventional FLCD is supported by a host computer and an external frame buffer memory. In order to display a color image on the FLCD, a frame of image data is transferred from the host computer to the external frame buffer memory. The external frame buffer memory supplies multi-bit pixel data to each pixel in the FLCD. The color image represented by the frame of pixel data is displayed on the FLCD as a result of a sequential process of loading each pixel of the FLCD with its multi-bit pixel data from the external frame buffer memory. Typically, each pixel in the FLCD has a single-bit storage register
10
and a pixel driver
12
, as depicted in FIG.
1
. Therefore, the external frame buffer memory must supply a series of single bits of pixel data to the pixels through the bit line
14
and word line
16
in order to display a particular color with a particular intensity at each pixel. The number of bits required for each pixel of FLCD to produce a desired color at a desired intensity may be 24 or more bits (e.g., three colors with eight bits of grayscale per color). In addition to the data that is required to display an image, equal and opposite DC balance data is required to be delivered to each pixel after the pixel has displayed a desired image. DC balance is utilized to extend the life of the liquid crystals and is well known in the art. While DC balance data is not visually displayed by the FLCD, the data is still supplied to the pixel from external circuitry.
Depending upon the transferred pixel data, light from the illuminator is either reflected to or deflected from the viewing optics. The pixels in the FLCD act as time-modulated micro mirrors in concert with the illuminator to produce the color image, which is determined by the values of the bits of pixel data. The quality of the color image is determined by the density of the pixels, the number of color-related bits within the pixel data transferred to each pixel, and the data transfer rate of the pixel data to the pixels. To display a high quality color image on the FLCD having the single-bit storage registers, a high bandwidth data link from the external frame buffer memory to the individual pixels is required for transferring the display data and the DC balance data. However, high bandwidth data links are expensive, potentially noisy, and require a great amount of power.
U.S. Pat. No. 4,432,610 to Kobayashi et al. (hereinafter Kobayashi) entitled “Liquid Crystal Display Device,” describes LCDs with various storage elements in the pixels. All of the storage elements described in Kobayashi are single-bit storage elements. A concern with single-bit storage registers in an LCD is the need to continually supply bits of pixel data at a high data transfer rate to develop a high resolution image on the LCD. Unless a sufficiently high data transfer rate is achieved, there will be limitations on the size of the LCD array, the display frame rate, and/or the number of bits of pixel data that may be transferred per frame. These physical limits affect the quality of the display image.
Another LCD with single-bit storage elements is described in U.S. Pat. No. 5,471,225 to Parks entitled “Liquid Crystal Display with Integrated Frame Buffer.” The single-bit storage elements in the LCD of Parks are static random access memory (SRAM) cells comprised of three transistors and two resistors. The SRAM cells allow the LCD to display an image for an indefinite amount of time without refreshing. However, the data transfer rate concern identified above for the LCDs of Kobayashi exists for the LCD of Parks.
U.S. Pat. No. 5,627,557 to Yamaguchi et al. (hereinafter Yamaguchi) entitled “Display Devices,” describes an improved pixel for an LCD. The pixel includes circuitry for storing a first bit of display data while displaying a second bit of display data. In addition, Yamaguichi discloses a circuit integrated into the pixel cell that includes a sample-and-hold capacitor for holding a negative scanning signal which may be used for DC balancing. While DC balance data is held simultaneously with display data in the pixel cell, the DC balance data is created by external drive circuitry and transferred from an external frame buffer through the bit line of the pixel cell.
In view of the expense of high bandwidth links between the frame buffer and the display pixels and the large volume of display data required to generate high resolution video images, what is needed is a pixel cell that enables a reduction in the requirements of transferring display data and DC balance data to a pixel cell.
SUMMARY OF THE INVENTION
A method and an apparatus for reducing data transfer requirements to a pixel cell involve an array of pixels in which each pixel cell includes circuitry for generating its own DC balance data by utilizing display data that is transferred to the pixel from an external frame buffer or other source of the display data. Each pixel cell includes an initial storage node that branches into two separate storage nodes, with the first of the branched nodes being used to store data that is used to determine the display condition of the pixel and the second of the branched nodes being used to generate and hold the DC balance data. Once the display data has been utilized for display purposes by the pixel, the DC balance data is multiplexed to the pixel and the pixel is driven according to the DC balance data. By generating the DC balance data within the pixel cell, instead of transferring DC balance data to the pixel cell from an external source, the data transfer load to the pixel cell is reduced by approximately one-half.
In a preferred embodiment, a pixel cell with two bits of memory and DC balance generation capability includes an input storage block, a frame transfer block, a drive storage block, a DC balance block, a multiplexer, and a pixel driver. The input storage block includes a circuit for storing a bit of display data that is received from an external display buffer through a write bit line and a write word line. The input storage block consists of three NMOS transistors arranged to create a dynamic storage node. In addition, the input storage block provides a global reset signal that resets the dynamic storage node upon activation of the reset signal. Operation of the input storage block involves sending a puls
Agilent Technologie,s Inc.
Liang Regina
LandOfFree
Pixel cell with integrated DC balance circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pixel cell with integrated DC balance circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pixel cell with integrated DC balance circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2468504