Pixel array scanning circuitry for a solid state imaging apparat

Details Pixel array scanning circuitry for a solid state imaging apparat Pixel array scanning circuitry for a solid state imaging apparat

1991-05-10

1992-11-03

Groody, James J.

Facsimile and static presentation processing

Facsimile

Recording apparatus

35821311, 35821326, 35821331, H04N 314, H04N 5335

Patent

active

051610248

ABSTRACT:
A solid state imaging apparatus includes a pixel array composed of CMD pixels, and vertical and horizontal scanning circuits for sequentially selecting pixels in the pixel array by an X-Y address method so as to read output signals. The horizontal scanning circuit is constructed so that, prior to a reading period, the horizontal scanning circuit connects bit lines to a reference line of a reference potential for the amount of time equal to a 1-bit period or a bit period less than the number of horizontal pixels. Such construction limits an electric current flowing to the reference line, thereby inhibiting an increase in the potential of the reference line. The generation of a lateral smear is thus inhibited.

REFERENCES:
patent: 4751559 (1988-06-01), Sugawa et al.
patent: 4851177 (1989-07-01), Ohzu
patent: 4875091 (1989-10-01), Yamada et al.
patent: 4929994 (1990-05-01), Matsumoto
"MOS Area Sensor: Part II--Low-Noise MOS Area Sensor With Antiblooming Photodiodes", Shinya Ohba et al, IEEE Transactions on Electron Devices, vol. ED-27, No. 8, Aug. 1980, pp. 1682-1687.
"A New MOS Image Sensor Operating In A Non-Destructive Readout Mode", T. Nakamura et al, IEDM 1986, pp. 353-356.

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