Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-10-26
2004-06-08
Fourson, George (Department: 2826)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
Reexamination Certificate
active
06746933
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates to a semiconductor device for use in a semiconductor integrated circuit, and more particularly, to a pitcher-shaped active area for a field effect transistor having a widened top portion.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced without loss of device performance. Particularly, because the integration of semiconductor devices increases, there is a corresponding size reduction in field effect transistors (FETs).
FETs are the basic electrical devices of today's integrated circuits. Such transistors may be formed in conventional substrates (such as a silicon substrate), or in silicon-on-insulator (SOI) substrates for example. For example, a conventional metal oxide semiconductor field effect transistor (MOS FET) formed in a silicon substrate may include a gate oxide layer formed on the substrate, a gate formed on the gate oxide layer, spacers formed beside the gate on the gate oxide layer, and a doped source region and a doped drain region arranged on respective sides of a gate conductor in the substrate. The gate is separated from a channel (which is situated between the source and drain regions) by the gate oxide layer. Shallow trench insulator (STI), local oxidation of silicon (LOCOS), or poly-buffered LOCOS isolations are usually employed to provide for isolation of adjacent transistors.
Conventionally, in the process of fabricating a conventional FET, lithography is used to form an opening for an active area for the FET, then etching is carried out to form the actual active area for the FET in the silicon substrate. However, there are some problems associated with the conventional FET active area and the conventional method steps for forming such a FET active area. First, the top width of the active area structure of the FET is generally defined by lithography, and therefore, is limited by the smallest ground rules for exposure with a lithography tool. Second, because the top corners of the active area are angular and not rounded, the top angular corners of the active area create a higher electric field between the gate conductor and the active area, which translates into a lower threshold voltage at the angular corners than at the back of the FET.
Additionally, when the FET is operated, an electric field is generated by applying a voltage to the gate. The electrical field is used to control a channel, which is between the source region and the drain region. For example, if channel is turned on, the electrons flow from the source region to the drain region. In contrast, if the channel is turned off, the electrons cannot flow between the source region and the drain region. Therefore, the on or off state of the channel controls the connection or disconnection of the circuit. In current device designs for logic and memory devices, a high transistor on-current is essential for fast charge transfer and therefore, increased switching speed of the logic or memory device. One conventional method of increasing transistor on-current is by reducing the effective channel length by reduction of the lithographic gate length. However, his conventional method necessitates an increase in channel doping combined with source-drain engineering for highly doped shallow extensions in device design in an attempt to try and avoid transistor short-channel effects and higher serial resistance.
Thus, there is a need for an improved active area structure for a FET having an increased transistor on-current, a decreased transistor serial resistance, and a decreased contact resistance.
DISCLOSURE OF THE INVENTION
The present invention provides an improved pitcher-shaped active area for a field effect transistor (FET) that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance without any complex device engineering. In contrast to the conventional practice of continually increasing device density in integrated circuits by narrowing especially the width of active area sites and reducing the gate length, the present invention widens the top portions of active area sites keeping the same gate length or slightly increasing it, thereby simplifying source-drain engineering. Thus, the present invention maintains the benefit of a wider active area, which maintains or increases transistor on-current.
In association with one embodiment of present invention, a pitcher-shaped active area structure for a FET includes a semiconductor substrate. Formed into the substrate are at least two shallow trench insulator (STI) structures that isolate the FET and define an active area structure. The active area structure includes a widened top portion; and a bottom portion, wherein the widened top portion has a larger width than the bottom portion.
The present invention also provides an improved fabrication method for forming the pitcher-shaped active area for a FET. In association with one embodiment of present invention, a method is disclosed wherein a pitcher-shaped active area is formed by implementing a step to form shallow trench insulator (STI) divots followed by a step to migrate substrate material into the STI divots, thereby forming a widened top portion of the active area structure. The fabrication methods of the present invention form the pitcher-shaped active area without the use of lithography, and therefore, are not limited by the smallest ground rules for exposure with a lithography tool. Furthermore, the migration step may cause rounded comers in the widened top portion of the active area structure, thereby creating a lower electric field between the gate conductor and the active area. The lower electric field translates into a threshold voltage at the rounded corners that approaches or is equivalent to the threshold voltage at the back of the FET.
REFERENCES:
patent: 4565584 (1986-01-01), Tamura et al.
patent: 4881105 (1989-11-01), Davari et al.
patent: 4952446 (1990-08-01), Lee et al.
patent: 5932893 (1999-08-01), Miyanaga et al.
patent: 5956598 (1999-09-01), Huang et al.
patent: 5989969 (1999-11-01), Watanabe et al.
patent: 6010797 (2000-01-01), Tomita et al.
patent: 6051458 (2000-04-01), Liang et al.
patent: 6069058 (2000-05-01), Hong
patent: 6100132 (2000-08-01), Sato et al.
patent: 6143635 (2000-11-01), Boyd et al.
patent: 6159823 (2000-12-01), Song et al.
patent: 6165841 (2000-12-01), Kim et al.
patent: 6184108 (2001-02-01), Omid-Zohoor et al.
patent: 6194755 (2001-02-01), Gambino et al.
patent: 6228727 (2001-05-01), Lim et al.
patent: 6245637 (2001-06-01), Tsai
patent: 6271100 (2001-08-01), Ballantine et al.
patent: 6331469 (2001-12-01), Park et al.
patent: 2002/0022344 (2002-02-01), Kang et al.
Wolf S., “Silicon Processing for the VLSI-ERA: vol. 1-Process Technology”, 1986, Lattice Pr., vol. 1, p. 531-533.*
Matsuda et al., “Novel Corner Rounding Process for Shallow Trench Isolation utilizing MSTS (Micro-Structure Transformation of Silicon”, Dec. 6-9, 1998, Electron Devices Meeting, IEDM Technical Digest., Internationa, p. 137-140.*
Sato et al., “Trench Transformation Technology using Hydrogen Annealing for Realizing Highly Reliable Device Structure with Thin Dielectric Films”, Jun. 9-11, 1998, VLSI Technology, Symposium on VLSI Technology Digest of Technical Papers, p. 206-207.
Beintner Jochen
Divakaruni Rama
Faltermeier Johnathan
Flaitz Philip L.
Gluschenkov Oleg
Capella Steven
Fourson George
Schmeiser Olsen & Watts
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