Pipelined video encoder architecture

Details Pipelined video encoder architecture Pipelined video encoder architecture

1993-05-26

1997-01-07

Ramirez, Ellis B.

Boots, shoes, and leggings

G06F 1700

Patent

active

055923992

ABSTRACT:
A system and method is provided for encoding data wherein contiguous data values represent a video image. Three contiguous data values are applied to a loop filter to provide digital filtering of the data values. A frame differencing device performs a subtraction operation upon one of the three contiguous data values simultaneously with the performance of a filtering operation upon another one of the three contiguous data values. Additionally, a discrete cosine transform device performs transform operations upon the third contiguous data value simultaneously with the performance of the digital filtering and the frame differencing operation upon the other two contiguous data values. Because the loop filter is a multipass device the frame differencing device and the discrete cosine transform device must wait while some filtering operations are performed. As soon as one of the contiguous values is applied to the output of the digital filtering device it is operated upon by the frame differencing device. When the frame differencing device is done with this value the discrete cosine transform device begins operating upon the output of the frame differencing device and the frame differencing device operates on the next contiguous data value from the loop filter. A discrete cosine transform system is provided for performing discrete cosine transforms on matrices of input video data.

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patent: 5045940 (1991-09-01), Peters et al.
Mandalia et al; "Flexible Hardware Archictecture for Multi-Media Communication Processing"; IEEE. 1989.

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