Pipelined vector processor for executing recursive instructions

Details Pipelined vector processor for executing recursive instructions Pipelined vector processor for executing recursive instructions

1988-03-30

1990-10-30

Zache, Raulfe B.

Boots, shoes, and leggings

3642318, 36423221, G06F 938, G06F 15347

Patent

active

049673505

ABSTRACT:
A vector computer includes memory 11 for storing vector data, and arithmetic unit 12 for sequentially reading out the vector data from memory 11, performing vector processing based on a pipeline system, and storing an operation result in memory 11. The vector computer further includes read/write controller 13 for storing white addresses of the memory at which results of operations being performed in stages of a pipeline are to be written, comparing the write addresses with a read address generated by arithmetic unit 12, and when at least one of the write addresses coincides with the read address, detecting that data designated by the read address is being operated in any stage of the pipeline, i.e., is not determined yet, thereby inhibiting reading of the data designated by the read address from memory 11.

REFERENCES:
patent: 4435765 (1984-03-01), Uchida et al.
patent: 4525796 (1985-06-01), Omoda et al.
patent: 4641275 (1987-02-01), Hatakeyama et al.
patent: 4757444 (1988-07-01), Aoyama et al.
patent: 4789925 (1988-12-01), Lahti
patent: 4853890 (1989-08-01), Abe et al.
P. M. Kogge: "The Architecture of Pipelined Computers", 1981, pp. 220-255, section 6.2: Interinstruction Dependencies and Hazards, Hemisphere Publishing Corp., New York, U.S.: *pp. 220-221, line 4; p. 222, lines 19-41*.
Patent Abstracts of Japan, vol. 7, No. 42 (P-177)[1187], Feb. 19, 1983; & JP-A-57 193 842 (Hitachi Seisakusho K.K.) 11-29-1982.

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