Pipelined SIMD-systolic array processor and methods thereof

Details Pipelined SIMD-systolic array processor and methods thereof Pipelined SIMD-systolic array processor and methods thereof

1994-06-15

1997-08-19

Coleman, Eric

Boots, shoes, and leggings

364DIG1, 36472412, 36472801, 3642319, 395376, 39580011, G06F 1580

Patent

active

056597800

ABSTRACT:
A pipelined SIMD-systolic array processor and its methods, mainly comprising a number of processing elements constructed as array architecture, multiport memory, registers, multiplexers, and controller, wherein the registers and multiplexers are connected for transferring data between the multiport memory and processing elements, the methods thereof uses a way which combines both broadcasting and systolic structures for transferring data into and out each processing element, and moreover, the method uses the controller to manipulate data transferring and the operation of each processing element for various functions; the array processor can have a faster processing speed and, through using a multiport memory, each processing element requires only a small amount of storage, and therefore, the array processor can use memory in a more efficient way.

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McWhirter et al., "On the Formal Derivation of a Systolic Array for Recursive Least Squares Estimation", IEEE, 1994, pp. 329-332.
Shimokawa et al., "A Parallel ASIC VLSI Neurocomputer For a Large Number of Neurons and Billion Connections Per Second Speed", IEEE, 1991, pp. 2162-2167.

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