Pipelined read write operations in a high speed frame buffer sys

Details Pipelined read write operations in a high speed frame buffer sys Pipelined read write operations in a high speed frame buffer sys

1993-10-29

1996-07-23

Weldon, Ulysses

Computer graphics processing and selective visual display system

Display peripheral interface input device

Light pen for fluid matrix display panel

345189, 345190, G09G 102

Patent

active

055394302

ABSTRACT:
A frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, row addressing decoding apparatus and column address decoding apparatus for selecting memory cells positioned in the array, apparatus for transferring a row address to the row addressing decoding apparatus upon the assertion of a row address strobe signal, apparatus for transferring a column address to the column address decoding apparatus for decoding upon the assertion of a first column address strobe signal, apparatus for latching a column address and any data necessary to complete the access during the first column address strobe signal, apparatus for accessing the particular column the address of which has been latched during the latching of a next subsequent address of a column to be accessed along with any data necessary to complete the next access during the next subsequent column address strobe signal following the first column address strobe signal.

REFERENCES:
patent: 4991110 (1991-02-01), Hannah
patent: 5017914 (1991-05-01), Uchida
patent: 5309173 (1994-05-01), Izzi
patent: 5355150 (1994-10-01), Murakami

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