Pipelined read architecture for memory

Details Pipelined read architecture for memory Pipelined read architecture for memory

1996-09-18

1997-11-04

Zarabian, A.

Static information storage and retrieval

Addressing

Plural blocks or banks

3652335, 36518905, G11C 804

Patent

active

056847521

ABSTRACT:
A memory device having a memory array is described. The memory device has a sensing stage to sense data stored within the memory array. The memory device also has an output stage to output the data stored within the memory array that has been sensed by the sensing stage. The sensing stage and the output stage are separated so that data associated with a first address within the memory array can be sensed while data associated with a second address within the memory array can be output.

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