Pipelined pyramid processor for image processing systems

Details Pipelined pyramid processor for image processing systems Pipelined pyramid processor for image processing systems

1997-04-15

1999-10-05

Au, Amelia

Image analysis

Image enhancement or restoration

Image filter

382261, 36472405, G06K 940

Patent

active

059636750

ABSTRACT:
A pipelined parallel processor (PPP) integrated onto a single integrated circuit. The PPP includes a filtering unit, internal routing circuitry such as a crosspoint switch, an internal frame store controller, and one or more function circuits. The function circuits may be, for example, arithmetic units, lookup tables, timing compensators, adders/subtractors, statistics modules, image shifting circuitry, and other useful processing devices. The components of the PPP are interconnected with the crosspoint switch which routes data between the frame store controller, the filtering unit, function circuits, external input channels, and external output channels.

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Copy of International Search Report dated Aug. 4, 1997, from corresponding international application PCT/US96/05426.
(1) SMI ASSP IP90C61, Enhanced Frame Memory Controller (EFMC, Description Form, Sumitomo Industries, Ltd., (Available 4th Qtr 1995). (1 pp).
(2) SMI ASSP IP90C20, Median/Max/Min Filter (RKFil), Description Form, Sumitomo Metals, (2pp).

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