Pipelined programming of non-volatile memories using early data

Details Pipelined programming of non-volatile memories using early data Pipelined programming of non-volatile memories using early data

2007-11-27

2007-11-27

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Floating gate

Disturbance control

C365S185120, C365S185170, C365S185030, C365S185220

Reexamination Certificate

active

11462946

ABSTRACT:
The present invention presents techniques whereby a memory system interrupts a programming process and restarts it including additional data. More specifically, when a memory system programs data into a group of cells together as programming unit, programming can begin with less than the full data content which the group can hold. In one embodiment, the present invention allows overlapped programming of upper and lower data pages, where once the memory begins programming the lower logical data page, if data is received for the upper page assigned to the same physical page, programming is interrupted and recommenced with the concurrent programming of both the upper and the loser pages. In a complimentary embodiment, when a page contains multiple sectors of data, programming of the physical page can begin when one or more, but less than all, of the sectors forming the corresponding logical page have been received, stopped and restarted to include additional sectors of the page.

REFERENCES:
patent: 5274646 (1993-12-01), Brey et al.
patent: 5465235 (1995-11-01), Miyamoto
patent: 5586285 (1996-12-01), Hasbun
patent: 5734816 (1998-03-01), Niijima et al.
patent: 5822245 (1998-10-01), Gupta et al.
patent: 5862099 (1999-01-01), Gannage et al.
patent: 5890192 (1999-03-01), Lee et al.
patent: 5893135 (1999-04-01), Hasbun et al.
patent: 5969986 (1999-10-01), Wong et al.
patent: 6021463 (2000-02-01), Belser
patent: 6029233 (2000-02-01), Abily et al.
patent: 6040997 (2000-03-01), Estakhri
patent: 6266273 (2001-07-01), Conley et al.
patent: 6282624 (2001-08-01), Kimura et al.
patent: 6295619 (2001-09-01), Hasbun
patent: 6317371 (2001-11-01), Katayama et al.
patent: 6330185 (2001-12-01), Wong et al.
patent: 6374337 (2002-04-01), Estakhri
patent: 6388920 (2002-05-01), Katayama et al.
patent: 6421279 (2002-07-01), Tobita et al.
patent: 6426893 (2002-07-01), Conley et al.
patent: 6449625 (2002-09-01), Wang
patent: 6456528 (2002-09-01), Chen
patent: 6490649 (2002-12-01), Sinclair
patent: 6522586 (2003-02-01), Wong
patent: 6525952 (2003-02-01), Araki et al.
patent: 6560143 (2003-05-01), Conley et al.
patent: 6581142 (2003-06-01), Jacobs
patent: 6996003 (2006-02-01), Li et al.
patent: 7120051 (2006-10-01), Gorobets et al.
patent: 2001/0040826 (2001-11-01), Lakhani
patent: 2002/0126528 (2002-09-01), Conley et al.
patent: 2003/0065899 (2003-04-01), Gorobets
patent: 2003/0070036 (2003-04-01), Gorobets
patent: 2003/0099134 (2003-05-01), Lasser et al.
patent: 2003/0123295 (2003-07-01), Elmhurst et al.
patent: 2003/0137888 (2003-07-01), Chen et al.
patent: 2003/0163629 (2003-08-01), Conley et al.
patent: 2003/0169630 (2003-09-01), Hosono et al.
patent: 2003/0174555 (2003-09-01), Conley et al.
patent: 2004/0001356 (2004-01-01), Kawamura et al.
patent: 2004/0027857 (2004-02-01), Ooishi
patent: 2004/0160829 (2004-08-01), Tsujikawa et al.
patent: 2004/0210729 (2004-10-01), Horii et al.
patent: 2004/0237000 (2004-11-01), Keays
patent: 2006/0126393 (2006-06-01), Li
patent: 2006/0126394 (2006-06-01), Li
patent: 2006/0156189 (2006-07-01), Tomlin
patent: 0615184 (1994-09-01), None
patent: 1280161 (2003-01-01), None
patent: 2 034 942 (1980-06-01), None
patent: 5282883 (1993-10-01), None
patent: 11003290 (1999-11-01), None
patent: WO 98/44420 (1998-10-01), None
patent: WO 00/49488 (2000-08-01), None
patent: WO 00/67137 (2000-11-01), None
patent: WO 02/49039 (2002-06-01), None
patent: WO 02/058074 (2002-07-01), None
patent: WO 03/029951 (2003-04-01), None
patent: WO 03/069627 (2003-08-01), None
Nakamura et al., “A Novel Sense Amplifier for Flexible Voltage Operation NAND Flash Memories,” 1995Symposium on VLSI Circuits Digest of Technical Papers, Jun. 8-10, 1995, pp. 71-72.
Srisa-an et al., “Performance Enhancements to the Active Memory System,”2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors, Sep. 16-18, 2002, pp. 249-256.
Lee et al., “High-Performance 1-Gb NAND Flash Memory with 0.12-μm Technology,”Journal of Solid-State Circuits, Nov. 2002, vol. 37, No. 11, pp. 1502-1509.
Imamiya et al., “A 125-mm21-Gb NAND Flash Memory with 10/Mbyte/s Program Speed,”IEEE Journal of Solid State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1493-1501.
Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration for International Application No. PCT/US2005/016341 mailed Oct. 19, 2005, 12 pages.
Notification of Transmittral of the International Search Report and the Written Opinion of the International Searching Authority, or the Delcaration for International Application No. PCT/US2005/043020 mailed May 10, 2006, 9 pages.
Listing of Pending Claims for International Application No. PCT/US2005/043020, 7 pages.

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