Pipelined processor with two tier prefetch buffer structure and

Details Pipelined processor with two tier prefetch buffer structure and Pipelined processor with two tier prefetch buffer structure and

1995-05-26

1997-10-21

Lall, Parshotam S.

395383, 395380, 395464, G06F 938

Patent

active

056805640

ABSTRACT:
A method and apparatus for prefetching instructions in a pipelined processor including first and second prefetch buffers arranged in a two tier system. As instruction bytes are fetched from cache memory or external memory, those instruction bytes from memory for which there is space in the first level buffer are loaded therein, and, simultaneously, those valid instruction bytes in the second tier buffer for which there is room in the first tier buffer are also loaded into the first tier buffer. Those instruction bytes from memory for which there is not currently room in the first tier buffer are loaded into the second tier buffer. The second tier buffer is also used as a buffer for loading the instruction cache memory from the external memory.

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