Pipelined parallel-serial architecture for a modified least mean

Details Pipelined parallel-serial architecture for a modified least mean Pipelined parallel-serial architecture for a modified least mean

1997-08-18

1999-12-28

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 1710

Patent

active

060094486

ABSTRACT:
A modified least mean squares adaptive filter method and apparatus is disclosed. The filter coefficients used to perform the FIR multiplications in a least mean squares adaptive filter are time dependent upon a time index. Each tap of the FIR section utilizes a coefficient at a different time index. This allows an implementation in hardware that is modular and easy for implementation in VLSI technologies. In addition, an improve multiplier and accumulator is disclosed for use in implementing the improved least squares adaptive filter.

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Chin-Liang Wang, "Bit-Serial VLSI Implementation of Delayed LMS Adaptive FIR Filters," IEEE Transactions on Signal Processing, vol. 42, No. 8, Aug. 1994, 2169-2175.

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