Pipelined oversampling A/D converter

Details Pipelined oversampling A/D converter Pipelined oversampling A/D converter

1999-01-29

2001-03-06

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S126000

Reexamination Certificate

active

06198417

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to the field of A/D converters, and in particular to a pipelined oversampling A/D converter.
Oversampled &Dgr;&Sgr; modulation is a technique that is commonly used for implementing high precision analog-to-digital (A/D) converters. It involves converting an analog input into a coarse digital code at a frequency much higher than the Nyquist rate, and then digitally decimating this code to produce a higher resolution, lower data rate result.
Single-loop systems, such as that illustrated in
FIG. 1
, are the simplest example of &Dgr;&Sgr; converters.
FIG. 1
is a schematic block diagram of a first order &Dgr;&Sgr;A/D converter
100
that includes an analog modulator
102
and a digital decimator
104
. The modulator
102
consists of a discrete-time integrator
106
, a coarse analog-to-digital converter (ADC)
108
, and a coarse digital-to-analog converter (DAC)
110
, connected in a feedback configuration. The ADC and DAC are often 1-bit elements. The modulator's front end performs analog operations, while its output is digital. The decimator
104
is strictly digital and consists of a lowpass filter
112
followed by a downsampler
114
.
The modulator can be analyzed by modeling ideal quantization noise and other sources of non-ideal noise, introduced by the feedforward ADC, as an additive error, e
r
. The modulator's output is then described by the difference equation
w
r
[n
]=s
i
[n
−1]+e
r
[n
]−e
r
[n
−1].  (1)
Node w
r
contains signal information, unchanged except for a delay, and the 1st-order difference of feedforward ADC quantization noise.
FIG. 2
shows the time-domain characteristics of the modulator's output w
r
. The duty cycle represents the converter's average analog input. An input greater than half of the full-scale value results in a stream of digital bits with more 1s than 0s. Although large error is introduced into each value of w
r
by the 1-bit quantization shown here, feedback ensures that the average, or duty cycle, of w
r
tracks that of the analog input, s
i
. Similarly, a signal less than half of the full-scale value results in more 0s than 1s.
Differentiation of the quantization noise, e
r
, is one form of noise shaping. A frequency domain representation of this process is illustrated in FIG.
3
.
FIG. 3
is a graph of frequency-domain characteristics of &Dgr;&Sgr; modulation. Shaping reduces noise within the signal bandwidth. In this simple model, it is assumed that e
r
is uniformly distributed in frequency before it experiences noise shaping. At the modulator's output, w
r
has a z-transform of
W
r
=S
i
·z
−1
+E
r
·(1
−z
−1
).  (2)
The spectral distribution of e
r
is shaped as indicated in FIG.
3
. Quantization noise energy is reduced at low frequencies but is increased at high frequencies. The response of a simple sinc
2
decimation filter is shown in the figure. Input signals are restricted to frequencies within the decimator's passband, typically a small fraction of the modulator's total bandwidth. The ratio between modulator sampling frequency and input Nyquist rate is referred to as the oversampling ratio.
The modulator's output, w
r
, contains input signal components as well as modulation and circuit noise. The decimation filter attenuates its energy outside of the signal bandwidth so that when w
r
is resampled at a lower rate, aliasing does not corrupt the signal. Only noise within the signal bandwidth influences the converter's result. In the final stages of decimation, downsampling converts the filter's output from a series of low resolution, high frequency words to a series of higher-resolution words at the Nyquist rate. Resolution in the converter's output words is increased by 9 dB, or 1.5 bits, for every doubling of the oversampling ratio.
The 1st-order architecture described above is the simplest example of an oversampling &Dgr;&Sgr; modulator. It contains only a single feedback loop. However, single-loop modulators require large oversampling ratios to achieve high resolution. The need for a large oversampling ratio is alleviated by use of 2nd-order &Dgr;&Sgr; modulation.
FIG. 4
is a schematic block diagram of a second order &Dgr;&Sgr; system
400
which includes a modulator
402
and a decimator
404
. The system contains two nested feedback loops within its modulator. The inner loop is similar to that of a 1st-order modulator, with an integrator
406
, a coarse ADC
408
, and a coarse DAC
410
. The outer loop adds a second analog integrator
412
, cascaded with the first integrator, and an outer feedback path. The decimator
404
is also modified to include first
414
, second
416
and third
418
stages of digital accumulation with a downsampler
420
.
In this architecture, the modulator's output has a z-transform of
W
r
=S
i
·z
−2
+E
r
·(1
−z
−1
)
2
,  (3)
which contains delayed signal information plus the 2nd-order difference of quantization and other errors in the feedforward path. In comparison to first order, this modulator is capable of greater resolution for the same oversampling ratio because its higher-order noise shaping leaves less noise energy within the signal band. Resolution in the converter's output word is improved by 15 dB, or 2.5 bits, for every doubling of the oversampling ratio.
&Dgr;&Sgr; techniques offer a number of advantages that make them well suited for high-resolution A/D conversion. First, high resolution is achieved despite inaccuracies of internal circuit components such as the ADC. In contrast, component imperfections generally limit non-oversampling architectures to about 12-bit resolution. Second, high resolution is achieved from an ADC with only a few levels and these levels do not require great precision. The ADC in a 1-bit system is particularly simple to implement because it consists of a single comparator. A third advantage is that high resolution is possible from a DAC with only a few levels. Although full resolution is required from the placement of these levels, 1-bit systems are capable of excellent linearity because they contain only two DAC levels and variation in the placement of these does not introduce nonlinearity. A final advantage is that antialias filtering at the converter's input is simplified because the decimator serves as a digital antialias filter.
The advantages of &Dgr;&Sgr; techniques arise through a series of tradeoffs. First, higher accuracy is achieved at the expense of a drastic increase in the number of operations required. The number of operations performed by non-oversampling architectures, such as successive approximation, increases linearly with converter bits, whereas for A) converters it increases exponentially. In a second tradeoff, &Dgr;&Sgr; converters achieve simplicity in their analog circuitry by moving processing complexity into the digital domain. Decimation filters with a flat passband response and a sharp cutoff transition often constitute a majority of the complexity, chip area, and power dissipation of such a device. In a third tradeoff, resolution is improved by a longer decimator impulse response at the expense of increased converter settling time.
Finally, &Dgr;&Sgr; techniques include an inherent tradeoff between speed and resolution, whereby these characteristics are not independently adjustable. An increase in the oversampling ratio improves resolution, but reduces the data rate. Similarly, a decrease in the oversampling ratio improves the data rate at the expense of resolution. Data rates are limited because the modulator must operate over many clock cycles to produce a single result. This speed-resolution tradeoff has been the subject of much attention. Data rates are improved by higher-order modulators, but those of greater than second order are susceptible to instability and have increased circuit complexity. Data rates are improved by use of multi-bit qua

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