Pipelined multiplier for signed multiplication

Details Pipelined multiplier for signed multiplication Pipelined multiplier for signed multiplication

1993-11-09

1995-04-04

Mai, Tan V.

Boots, shoes, and leggings

G06F 752

Patent

active

054043239

ABSTRACT:
A pipelined multiplier for signed multiplication has a plurality of pipeline stages, each of which includes a row of registers, and a row of operating cells. The operating cells includes a plurality: of AND gates, NAND gates, half adders, and full adders connected to perform the signed multiplication according to the Hatamian-Cash algorithm. The pipelined multiplier is characterized by that the most significant bit of the product is directly obtained from the previous less significant bit of the product.

REFERENCES:
patent: 3866030 (1975-02-01), Baugh et al.
patent: 4736335 (1988-04-01), Barkan
patent: 5181184 (1993-01-01), Shim et al.
Hatamian et al, "A 70-MHz 8-bit.times.8-bit Parallel Pipelined Multiplier in 2.5 .mu.m CMOS" IEEE Journal of Solid-State Circuits, vol. SC-21, No. 4 pp. 505-513 Aug. 1986.

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