Pipelined multi-stage data processor including an operand bypass

Details Pipelined multi-stage data processor including an operand bypass Pipelined multi-stage data processor including an operand bypass

1989-02-17

1992-09-15

Lee, Thomas C.

Boots, shoes, and leggings

364DIG1, 364DIG2, 36494834, 3642613, 3642318, G06F 938

Patent

active

051485290

ABSTRACT:
A pipelined multi-stage data processor has a bypass circuit which is enabled when a memory reading request signal from the operand fetch stage and a memory writing request signal from the execution stage are simultaneously received by a control device with respect to an identical location in the memory. The bypass circuit operates to cause the write data to be written into the memory to be directly transferred to the fetch stage so that the memory reading operation is performed without actually accessing the memory.

REFERENCES:
patent: 4476525 (1984-10-01), Ishii
patent: 4477872 (1984-10-01), Losq et al.
patent: 4644466 (1987-02-01), Saito
patent: 4858104 (1989-08-01), Matsuo et al.
"Branch Prediction Strategies and Branch Target Buffer Design", Lee et al., Computer, vol. 17, No. 1, Jan. 1984.

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