Pipelined microprocessor with fast non-selective correct...

Details Pipelined microprocessor with fast non-selective correct... Pipelined microprocessor with fast non-selective correct...

2011-07-12

2011-07-12

Treat, William M (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction fetching

C712S234000

Reexamination Certificate

active

07979675

ABSTRACT:
A microprocessor includes a register that stores a state and a fetch unit that fetches instructions of a program. The program includes a first instruction followed non-immediately by a second instruction. The first instruction instructs the microprocessor to update the state in the register. The second instruction is a conditional branch instruction that specifies a branch condition based on the register state. The fetch unit dispatches the first instruction for execution but refrains from dispatching the second instruction for execution. Execution units receive the first instruction from the fetch unit and responsively update the register state. The fetch unit non-selectively correctly resolves the conditional branch instruction based on the register state when the execution units have updated the register state. The fetch unit also non-selectively refrains from sending the conditional branch instruction to the execution units to be resolved regardless of whether the execution units have updated the register state.

REFERENCES:
patent: 5805876 (1998-09-01), Bose et al.
patent: 6496975 (2002-12-01), Slinger
patent: 6598153 (2003-07-01), Flachs et al.
patent: 6757816 (2004-06-01), Yoaz et al.

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