Pipelined, line buffered real-time color graphics display system

Details Pipelined, line buffered real-time color graphics display system Pipelined, line buffered real-time color graphics display system

1984-07-30

1987-04-14

Brigance, Gerald L.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340703, 340750, 364521, G09G 114

Patent

active

046582479

ABSTRACT:
A color graphics system for displaying a plurality of polygons, based upon polygon commands supplied by a host computer. The system accepts the commands from the host and circulates them in a circular queue past a polygon processor or "painter's station" which examines each to see if it is on the line currently being processed. If the polygon is on the line, a line command or "micropainter" is generated and placed in a pipeline comprising a plurality of microprocessors, one for each picture element ("pixel") in the video scan line. The micropainters are passed from processor to processor down the pipeline, in synchronization with the video scan. Each pixel processor examines the micropainter and stores its color if the painter affects the pixel on the scan line which is assigned to that processor, and, in one embodiment, if the micropainter is painting a polygon which is higher (less in depth) than the last polygon whose color was stored in the processor. A special command, called a "microinspector" is introduced into the pipeline once each scan, and causes each pixel processor in turn to output its stored video information to a video refresh processor, which drives the display.

REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 4197590 (1980-04-01), Sukonick
patent: 4353061 (1982-10-01), Beck
patent: 4496944 (1985-01-01), Collmeyer et al.
Bechtolsheim, A. & Baskett, F., "High Performance Rastor Graphics for Microcomputer Systems" ACM 0-89791-021-4/80/0700-043.
Clark, J. & Hannah, M. "Distributed Processing in a High-Performance Smart Image Memory System" Lambda Fourth Quarter 1980, p. 40.
Cosman, M. & Schumacker, R. "System Strategies to Optimize CIG Image Content" Proceedings of the Image II Conference, Scottsdale, Ariz., 10 Jun. 1981.
Demetrescu, S. "High Speed Rasterization Using a Highly Parallel Smart Bulk Memory" Stanford U. Computer Systems Laboratory, Tech Report #83-244, Jun. 1983.
Fuchs, H. & Poulton, J. "Pixel-Planes: A VLSI-Oriented Design for a Raster Graphics Engine" VLSI Design Third Quarter, 1981, p. 20.
Fuchs, H. & Poulton, J. et al. "Developing Pixel-Planes, a Smart Memory-Based Raster Graphics System" Proceedings of the 1982 Conference on Advanced VLSI, Massachusetts Institute of Technology.
Gupta, S., Sproull, R. & Sutherland, I., "A VLSI Architecture for Updating Raster-Scan Displays" Computer Graphics, Aug. 1981, p. 71.
Whelar, D. "A Rectangular Area Filling Display System Architecture" Computer Graphics Jul. 1982, p. 147.
Whitted, T. "Hardware Enhanced 3-D Raster Display System" Proceedings: 7th Man-Computer Communications Conference p. 349, National Research Council of Canada, 1981.

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